Information security for aeronautical surveillance systems

• US 20060008087A1
• Filed: 07/08/2004
• Published: 01/12/2006
• Est. Priority Date: 07/08/2004
• Status: Active Grant

• Current Assignee: Honeywell International Inc.
• Original Assignee: Honeywell International Inc.
• Inventors: Olive, Michael L.
• Granted Patent: US 7,515,715 B2
• Time in Patent Office: Days
• US Class Current: 380/255
• CPC Class Codes: G01S 13/782 using multimoding or selective addressing
• CPC Class Codes: H04L 2209/12 Details relating to cryptographic hardware or logic circuitry
• CPC Class Codes: H04L 2209/20 Manipulating the length of blocks of bits, e.g. padding or block truncation
• CPC Class Codes: H04L 2209/34 Encoding or coding, e.g. Huffman coding or error correction
• CPC Class Codes: H04L 9/0618 Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
• CPC Class Codes: H04L 9/0866 involving user or device identifiers, e.g. serial number, physical or biometrical information, DNA, hand-signature or measurable physical characteristics

Abstract

A method and apparatus for encrypting a Mode-S extended squitter exploiting a provided key. The key includes a control key segment, an address key segment, a first message key segment, and a first parity/identity key segment. Adding modulo two the control segment to the control key segment produces an intermediate control segment. Adding modulo two the address segment to the address key segment produces an intermediate address segment. Adding modulo two the message segment to the first message key segment produces an intermediate message segment. Adding modulo two the parity/identity segment to the first parity/identity key segment produces an first intermediate parity/identity segment. Concatenating the intermediate control segment, the intermediate address segment, the intermediate message segment, and the intermediate parity/identity segment produces an intermediate extended squitter. Shifting the intermediate extended squitter according to a linear function shift register produces a shifted-intermediate parity/identity segment.

Claims

1. A method for encrypting a Mode-S extended squitter, the Mode-S extended squitter including an eight-bit control segment followed by a twenty-four bit sender address segment, a fifty-six-bit message segment and a twenty-four-bit parity/identity segment, the method comprising:

providing a key, the key including a control key segment, an address key segment, a first message key segment, and a first parity/identity key segment;

adding modulo two the control segment to the control key segment to produce an intermediate control segment;

adding modulo two the address segment to the address key segment to produce an intermediate address segment;

adding modulo two the message segment to the first message key segment to produce an intermediate message segment; and

adding modulo two the parity/identity segment to the first parity/identity key segment to produce an first intermediate parity/identity segment.

2. The method of claim 1 further comprises:

concatenating the intermediate control segment, the intermediate address segment, the intermediate message segment, and the intermediate parity/identity segment to produce an intermediate extended squitter; and

shifting the intermediate extended squitter according to a linear function shift register to produce a shifted-intermediate parity/identity segment.

3. The method of claim 2, wherein the key further includes a second message key segment, and a second parity/identity key segment.

4. The method of claim 3, further comprising:

adding modulo two the message segment to the second message key segment to generate an encrypted message segment.

5. The method of claim 4, further comprising:

adding modulo two the shifted-intermediate parity segment to the second parity key to generate a doubly-encrypted parity/identity segment.

6. The method of claim 5, further comprising:

concatenating the control segment, the address segment, the encrypted message segment and the doubly-encrypted parity/identity segment to produce an encrypted extended squitter.

7. A method for decrypting an encrypted extended squitter, the encrypted extended squitter consisting of an eight-bit control segment followed by a twenty-four bit address segment, a fifty-six-bit encrypted message segment, and, the twenty-four bit doubly-encrypted parity/identity segment, the method comprising:

providing a key, the key including a second message key segment, and a second parity/identity key segment;

adding modulo two the encrypted message segment to the second message key segment to produce an intermediate message segment; and

adding modulo two the doubly-encrypted parity segment to the second parity segment to produce a singly-decrypted parity segment.

8. The method of claim 7 further comprising concatenating the control segment, the address segment, the intermediate message segment, and the singly-decrypted parity/identity segment to produce a first intermediate extended squitter.

9. The method of claim 8, wherein providing a key further includes providing a control key segment, an address key segment, a first message key segment, and a first parity/identity key segment.

10. The method of claim 9, further comprising:

decrypting the first intermediate extended squitter to generate a second intermediate extended squitter consisting of an encrypted control segment, an encrypted address segment, an encrypted message segment and the singly-encrypted parity segment, the decrypting including;

adding modulo two the control segment to the control key segment to produce the encrypted control segment;

adding modulo two the address segment to the address key segment to produce the encrypted address segment; and

adding modulo two the intermediate message segment according to the first message key segment to produce the encrypted message segment.

11. The method of claim 10, further comprising:

generating a shifted reference address by adding modulo two a recipient address to the first parity/identity key segment.

12. The method of claim 10, further comprising:

decrypting the second intermediate extended squitter, the decrypting including;

adding modulo two the encrypted control segment to the first control key to produce a control segment;

adding modulo two the encrypted address segment to the first address key to produce a address segment; and

adding modulo two the encrypted message segment according to the first message key to produce a message segment.

13. A Mode-S encrypter, the encrypter configured to encrypt a composed Mode-S extended squitter including an eight-bit control segment followed by a twenty-four bit address segment, a fifty-six-bit message segment, and a twenty-four-bit parity/identity segment, the encrypter comprising:

a first encryption component configured to adding modulo two a extended squitter to a first encryption key segment to produce an intermediate extended squitter;

a linear function shift register to shift the intermediate extended squitter to generate a shifted, singly-encrypted parity segment;

a parity encryption component configured to further adding modulo two the shifted singly-encrypted parity/identity segment to a parity/identity encryption segment to generate an doubly-encrypted parity/identity segment; and

a message encryption component configured to adding modulo two the message segment to a message encryption key.

14. The encrypter of claim 13, the first encryption component comprising:

a extended squitter buffer configured to store the composed Mode-S extended squitter;

a first key buffer configured to store the first encryption key segment;

an intermediate buffer configured to store the intermediate extended squitter; and

an XOR gate configured to add modulo two the composed Mode-S extended squitter to the first encryption key segment thereby to generate the intermediate extended squitter in the intermediate buffer.

15. The encrypter of claim 13, the parity encryption component comprising:

a shifted-singly-encrypted parity buffer configured to store the shifted-singly encrypted parity segment;

a parity key buffer configured to store the parity key segment;

an encrypted parity buffer configured to store the doubly-encrypted parity segment; and

an XOR gate configured to add modulo two the shifted-singly encrypted parity to the parity key segment thereby to generate the doubly-encrypted parity segment in the encrypted parity buffer.

16. The encrypter of claim 13, the message encryption component comprising:

a message buffer configured to store the message segment;

a message key buffer configured to store message key segment;

an encrypted message buffer configured to store the encrypted message; and

an XOR gate configured to add modulo two the message segment to the message key segment thereby to generate the encrypted message in the encrypted message buffer.

17. The encrypter of claim 13, the encrypter further comprising an output buffer, the output buffer configured to store:

the control segment;

the address segment;

the encrypted message segment; and

the doubly-encrypted parity/identity segment.

18. A decrypter for decrypting an encrypted composed Mode-S extended squitter to reconstitute the composed Mode-S extended squitter, the encrypted composed Mode-S extended squitter including a control segment, an address segment;

an encrypted message segment, and a doubly encrypted parity segment, the decrypter comprising;

a first decryption component, the first decryption component configured to generate an intermediate encrypted extended squitter including an intermediate encrypted parity segment based upon the encrypted composed Mode-S extended squitter;

a parity encryption segment for generating a reference parity segment based upon the address segment;

an error detection and correction component for correcting errors in the intermediate extended squitter based upon the intermediate extended squitter and the reference parity segment and generating a corrected intermediate control segment;

a corrected intermediate address segment, and a corrected intermediate message segment; and

a second decryption component configured for decrypting the corrected intermediate control segment to produce an output, the output comprising a corrected control segment, a corrected address segment, and a corrected message segment.

19. The decrypter of claim 18, the first decryption component comprising:

a encrypted extended squitter buffer configured to store the encrypted extended squitter;

a second code segment buffer configured to store a second code key-segment;

a first code key segment buffer configured to store a first code key segment;

an first intermediate buffer configured to store a first intermediate extended squitter;

a second intermediate buffer configured to store a second intermediate extended squitter;

a first XOR gate configured to add modulo two the encrypted extended squitter stored in the encrypted extended squitter buffer to the a second padded key consisting of a 32 bit zero concatenated with the second key segment thereby to generate the first intermediate extended squitter in the first intermediate buffer; and

a second XOR gate configured to add modulo two the first intermediate segment stored in the first intermediate buffer with a padded first key segment, the padded second key segment consisting of the first key segment concatenated with a 24-bit zero, thereby to generate the second intermediate extended squitter in the second intermediate buffer.

20. The decrypter of claim 18, the parity encryption component comprising:

a reference buffer configured to store the reference segment;

a parity key buffer configured to store the parity key segment; and

an XOR gate configured to add modulo two a recipient address to the first parity/identity key segment thereby to generate the reference segment in the reference buffer.

21. The decrypter of claim 18, the parity encryption component comprising:

a first key buffer configured to store the first key segment;

a first output buffer configured to store the output; and

an XOR gate configured to add modulo two the corrected intermediate extended squitter with the first key segment thereby to generate the output in the output buffer.