Memory utilizing oxide-conductor nanolaminates

• US 20060008966A1
• Filed: 08/31/2005
• Published: 01/12/2006
• Est. Priority Date: 07/08/2002
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ahn, Kie Y., Forbes, Leonard
• Granted Patent: US 7,583,534 B2
• Time in Patent Office: Days
• US Class Current: 438/201
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: H01L 29/42332 with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Structures, systems and methods for floating gate transistors utilizing oxide-conductor nanolaminates are provided. One floating gate transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A floating gate is separated from the channel region by a first gate oxide. The floating gate includes oxide-conductor nanolaminate layers to trap charge in potential wells formed by different electron affinities of the oxide-conductor nanolaminate layers.

Claims

1. A method for operating a floating gate transistor array, comprising:

programming one or more floating gate transistors in the array, wherein each floating gate transistor includes a source region, a drain region, a channel region between the source and the drain regions, a floating gate separated from the channel region by a first gate oxide, and a control gate separated from the floating gate by a second gate oxide, wherein a floating gate region includes at least one oxide-conductor nanolaminate layer with at least one layer of a metal conductor, wherein the array includes a number of sourcelines coupled to the source regions of each floating gate transistor along rows in the array, and wherein the array includes a number of bitlines coupled to the drain region along rows in the array, and wherein programming the one or more floating gate transistors includes;

applying a first voltage potential to a drain region of the floating gate transistor;

applying a second voltage potential to a source region of the floating gate transistor; and

applying a control gate potential to the control gate of the floating gate transistor.

2. The method of claim 1, wherein applying a first voltage potential to the drain region of the floating gate transistor includes grounding the drain region of the floating gate transistor.

3. The method of claim 2, wherein applying a second voltage potential to the source region includes applying a high voltage potential (VDD) to a sourceline coupled thereto.

4. The method of claim 3, wherein applying a gate potential to the gate of the floating gate transistor includes applying a gate potential to the gate in order to create a conduction channel between the source and drain regions of the floating gate transistor.

5. The method of claim 1, wherein the method further includes reading one or more floating gate transistors, wherein reading the one or more floating gate transistors includes:

grounding the source region for an addressed floating gate transistor;

precharging the drain region for the addressed floating gate transistor to a fractional voltage of VDD; and

applying a gate potential of approximately 1.0 Volt to the floating gate for the addressed floating gate transistor such that a conductivity state of the addressed floating gate transistor can be compared to a conductivity state of a reference cell.

6. A method of operating a multistate memory, comprising:

writing to one or more vertical floating gate transistors arranged in rows and columns extending outwardly from a substrate and separated by trenches in a DRAM array, wherein each floating gate transistor in the DRAM array includes a source region, a drain region, a channel region between the source and the drain regions, a floating gate in the trenches separated from the channel region by a first gate oxide, and a control gate separated from the floating gate by a second gate oxide, wherein a floating gate region includes at least one oxide-conductor nanolaminate layer with at least one layer of a metal conductor, wherein the DRAM array includes a number of sourcelines formed in a bottom of the trenches between rows of the vertical floating gate transistors and coupled to the source regions of each floating gate transistor along rows of the vertical floating gate transistors, wherein along columns of the vertical floating gate transistors the source region of each column adjacent vertical floating gate transistors couples to the sourceline in a shared trench, and wherein the DRAM array includes a number of bitlines coupled to the drain region along rows in the DRAM array, and wherein programming the one or more vertical floating gate transistors includes;

biasing a sourceline for two column adjacent vertical floating gate transistors sharing a trench to a voltage higher than VDD;

grounding a bitline coupled to one of the drain regions of the two column adjacent vertical floating gate transistors in the vertical floating gate transistors to be programmed;

applying a gate potential to the control gate for each of the two column adjacent vertical floating gate transistors to create a hot electron injection into the floating gate of the vertical floating gate transistor to be programmed such that an addressed floating gate transistor becomes a programmed floating gate;

reading one or more vertical floating gate transistors in the DRAM array, wherein reading the one or more floating gate transistors includes;

grounding a sourceline for two column adjacent vertical floating gate transistors sharing a trench;

precharging the drain regions of the two column adjacent vertical floating gate transistors sharing a trench to a fractional voltage of VDD; and

applying a gate potential of approximately 1.0 Volt to the control gate for each of the two column adjacent vertical floating gate transistors sharing a trench such that a conductivity state of an addressed vertical floating gate transistor can be compared to a conductivity state of a reference cell.

7. The method of claim 6, wherein reading one or more vertical floating gate transistors in the DRAM array includes using a sense amplifier to detect whether an addressed vertical floating gate transistor is a programmed vertical floating gate transistor, wherein a programmed vertical floating gate transistor will not conduct.

8. The method of claim 6, wherein creating a hot electron injection into the floating gate of an addressed vertical floating gate transistor includes changing a threshold voltage for the vertical floating gate transistor by approximately 0.5 Volts.

9. The method of claim 6, wherein creating a hot electron injection into the floating gate of the addressed vertical floating gate transistor includes trapping a stored charge in the floating gate of the addressed vertical floating gate transistor of approximately 10¹² electrons/cm².

10. The method of claim 6, wherein creating a hot electron injection into the floating gate of the addressed vertical floating gate transistor includes trapping a stored charge in the gate insulator of the addressed vertical floating gate transistor of approximately 100 electrons.

11. The method of claim 6, wherein the method further includes using the vertical floating gate transistor as an active device with gain, and wherein reading a programmed vertical floating gate transistor includes providing an amplification of a stored charge in the floating gate from approximately 100 to 800,000 electrons over a read address period of approximately 10 ns.

12. A method for operating a floating gate transistor, comprising:

programming the floating gate transistor, including;

applying a first voltage potential to a drain region of the floating gate transistor;

applying a second voltage potential to a source region of the floating gate transistor;

applying a control gate potential to a control gate of the floating gate transistor; and

storing a programming charge on a floating gate that includes a metal conductor nanolaminate layer.

13. The method of claim 12, wherein storing a programming charge on a floating gate that includes a metal conductor nanolaminate layer includes storing a programming charge on a floating gate that includes a Tantalum Nitride (TaN) layer.

14. The method of claim 12, wherein storing a programming charge on a floating gate that includes a metal conductor nanolaminate layer includes storing a programming charge on a floating gate that includes a Titanium Nitride (TiN) layer.

15. The method of claim 12, wherein storing a programming charge on a floating gate that includes a metal conductor nanolaminate layer includes storing a programming charge on a floating gate that includes a Tungsten Nitride (WN) layer.

16. The method of claim 12, wherein storing a programming charge on a floating gate that includes a metal conductor nanolaminate layer includes storing a programming charge on a floating gate that includes a Niobium Nitride (NbN) layer.

17. The method of claim 12, wherein storing a programming charge on a floating gate that includes a metal conductor nanolaminate layer includes storing a programming charge on a floating gate that includes a Molybdenum Nitride (MoN) layer.

18. The method of claim 12, wherein storing a programming charge on a floating gate that includes a metal conductor nanolaminate layer includes storing a programming charge on a floating gate that includes a Zinc-Oxide-Silicon (ZnOS) layer.

19. The method of claim 12, wherein storing a programming charge on a floating gate that includes a metal conductor nanolaminate layer includes storing a programming charge on a floating gate that includes a Tungsten (W) layer.

20. The method of claim 12, wherein storing a programming charge on a floating gate that includes a metal conductor nanolaminate layer includes storing a programming charge on a floating gate that includes a Nickel (Ni) layer.

21. A method for operating a floating gate transistor, comprising:

programming the floating gate transistor, including;

applying a first voltage potential to a drain region of the floating gate transistor;

applying a second voltage potential to a source region of the floating gate transistor;

applying a control gate potential to a control gate of the floating gate transistor;

storing a programming charge on a floating gate that includes a metal conductor nanolaminate layer; and

reading the floating gate transistor.

22. The method of claim 21, wherein storing a programming charge on a floating gate includes storing a charge using hot electron injection by operating the transistor in a reverse direction.

23. The method of claim 21, wherein reading the floating gate transistor includes operating the transistor in a forward direction.

24. A method for operating an electronic system, comprising:

programming a floating gate transistor in a memory array, including;

applying a first voltage potential to a drain region of the floating gate transistor;

applying a second voltage potential to a source region of the floating gate transistor;

applying a control gate potential to a control gate of the floating gate transistor;

storing a programming charge on a floating gate that includes a metal conductor nanolaminate layer;

reading data from the floating gate transistor; and

transmitting the data to a processor within the electronic system.

25. The method of claim 24, wherein storing a programming charge on a floating gate includes storing a charge using hot electron injection by operating the transistor in a reverse direction.

26. The method of claim 24, wherein reading the floating gate transistor includes operating the transistor in a forward direction.

27. The method of claim 24, wherein applying a first voltage potential to the drain region of the floating gate transistor includes grounding the drain region of the floating gate transistor.

28. The method of claim 24, wherein applying a second voltage potential to the source region includes applying a high voltage potential (VDD) to a sourceline coupled thereto.