Semiconductor assemblies, methods of forming structures over semiconductor substrates, and methods of forming transistors associated with semiconductor substrates

• US 20060008998A1
• Filed: 09/01/2005
• Published: 01/12/2006
• Est. Priority Date: 06/22/2000
• Status: Active Grant

• Current Assignee: Round Rock Research LLC
• Original Assignee: John T. Moore, Kevin L. Beaman
• Inventors: Moore, John T., Beaman, Kevin L.
• Granted Patent: US 7,371,647 B2
• Time in Patent Office: Days
• US Class Current: 438/287
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H10B 41/49 comprising different types of peripheral transistor
• CPC Class Codes: Y10S 257/90 MOSFET type gate sidewall insulating spacer

Abstract

The invention encompasses a method of forming a structure over a semiconductor substrate. A silicon dioxide containing layer is formed across at least some of the substrate. Nitrogen is formed within the silicon dioxide containing layer. Substantially all of the nitrogen within the silicon dioxide is at least 10 Å above the substrate. After the nitrogen is formed within the silicon dioxide layer, conductively doped silicon is formed on the silicon dioxide layer. The invention encompasses a method of forming a pair of transistors associated with a semiconductor substrate. First and second regions of the substrate are defined. A first oxide region is formed to cover the first region of the substrate, and to not cover the second region of the substrate. Nitrogen is formed within the first oxide region, and a first conductive layer is formed over the first oxide region. After the first conductive layer is formed, a second oxide region is formed over the second region of the substrate. A second conductive layer is formed over the second oxide region. The first conductive layer is patterned into a first transistor gate, and the second conductive layer is patterned into a second transistor gate. First source/drain regions are formed proximate the first transistor gate, and the second source/drain regions are formed proximate the second transistor gate. The invention also encompasses semiconductor assemblies.

Claims

1-35. -35. (canceled)

36. A method of forming a transistor, comprising:

forming a gate oxide over a semiconductor substrate, the gate oxide comprising an upper surface;

exposing the upper surface of the gate oxide to a nitrogen species in plasma conditions without biasing the semiconductor substrate, the exposing allowing penetration of nitrogen into the upper surface without any measurable amount of nitrogen penetrating substantially below the upper surface;

forming a gate of conductively-doped silicon over the gate oxide; and

forming source/drain regions in the semiconductor substrate operatively proximate the gate.

37. The method of claim 36, wherein the exposing comprises having the nitrogen species at least 12 inches from the upper surface of the gate oxide.

38. The method of claim 36, wherein the exposing comprises providing the nitrogen species as a highly activated nitrogen species, and further comprising limiting the penetration of nitrogen into the upper surface by enabling the highly activated nitrogen species to relax before the penetration.

39. The method of claim 36, wherein the gate oxide is less than 50 angstroms thick, and wherein substantially all of the nitrogen is provided in the top 10 angstroms of the gate oxide.

40. The method of claim 36, wherein the gate oxide is less than 40 angstroms thick, and wherein substantially all of the nitrogen is provided in the top 10 angstroms of the gate oxide.

41. The method of claim 36, wherein the exposing comprises having the nitrogen species at least 4 inches from the upper surface of the gate oxide.

42. The method of claim 36, wherein the conductively-doped silicon comprises conductively-doped amorphous silicon.

43. The method of claim 36, wherein the conductively-doped silicon comprises conductively-doped polycrystalline silicon.

44. The method of claim 36, wherein the gate of the conductively-doped silicon further comprises metals.

45. The method of claim 36, wherein the gate of the conductively-doped silicon further comprises silicides.

46. The method of claim 36, wherein the gate of the conductively-doped silicon further comprises suicides and metals.

47. The method of claim 36 further comprising forming a gate layer over the gate.

48. The method of claim 36 further comprising forming a conductive layer over the gate, the conductive layer comprising n-type doped silicon.

49. The method of claim 36, wherein the transistor comprises a NMOS device.

50. The method of claim 36, wherein the transistor comprises a PMOS device.