Circuit array substrate for display device and method of manufacturing the same

• US 20060009108A1
• Filed: 09/15/2005
• Published: 01/12/2006
• Est. Priority Date: 06/13/2002
• Status: Active Grant

• Current Assignee: Japan Display Central Incorporated (Japan Display Incorporated)
• Original Assignee: TFPD Corporation
• Inventors: Shigeno, Hirotaka
• Granted Patent: US 7,021,983 B2
• Time in Patent Office: Days
• US Class Current: 445/24
• CPC Class Codes: G02F 1/13452 Conductors connecting driver circuitry and terminals of panels
• CPC Class Codes: G02F 1/13458 Terminal pads
• CPC Class Codes: H05K 2201/09472 Recessed pad for surface mounting recess in pad H05K2201/09745; Recessed electrode of component
• CPC Class Codes: H05K 2201/09909 Special local insulating pattern, e.g. as dam around component
• CPC Class Codes: H05K 3/361 Assembling flexible printed circuits with other printed circuits

Abstract

A circuit array substrate 10 includes pixel and connecting edge sections 80 and 90. Connecting edge section 90 is provided with edge portions 5a and shoulder portions 55 of transparent thin resin film 5 over which terminal pins 101 of tape carrier packages (TCP) 100 are disposed. Terminal pins 101 are connected to connecting pads 14 at their contact portions 103. Shoulder portions 55 prevent a coated photoresist film from being excessive in depth and residues of the photoresist film from being left in the foot of edge face 5a in the step of forming metal reflective pixel electrodes. Thus, no residue of the metal film exists after its etching treatment in that step so that no electrical short circuits are caused between connecting pads 14 and adjacent terminal pins 101.

Claims

1-2. -2. (canceled)

3. A method of manufacturing a circuit array substrate for a display device comprising the steps of:

forming a wiring pattern over an insulation substrate and connecting pads connected to said wiring pattern;

forming a more than 1 μ

m thick insulation film except on said connecting pads where naked portions are made by treatments of coating a photoresist, exposure and development; and

forming electrically conductive pixel electrodes on said thick insulation film;

wherein said step of forming said thick insulation film uses a photomask with light blocking portions, full exposure portions to form said naked portions, and intermediate exposure portions to form shoulder portions.

4. The method of manufacturing a circuit array substrate for a display device according to claim 3, wherein said electrically conductive pixel electrodes include metal reflective pixel electrodes and said intermediate exposure portions are further used to form uneven patterns corresponding to said metal reflective pixel electrodes.

5. The method of manufacturing a circuit array substrate for a display device according to claim 4, wherein said intermediate exposure portion includes first semi-transparent members for said uneven patterns and second ones for said shoulder portions that are different in transparency from said first semi-transparent members thereby to make said uneven pattern one half in depth of said shoulder portions or less.

6. A method of manufacturing a circuit array substrate for a display device according to claim 4, wherein said intermediate exposure portion includes first apertures for said uneven patterns and second ones for said shoulder portions that are different in diameter from said first apertures thereby to make said uneven pattern one half in depth of said shoulder portions or less.