Wide dynamic range imager with selective readout

• US 20060011810A1
• Filed: 07/29/2004
• Published: 01/19/2006
• Est. Priority Date: 07/13/2004
• Status: Active Grant

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Micron Technology, Inc.
• Inventors: Otaka, Toshinori, Ando, Haruhisa
• Granted Patent: US 7,119,317 B2
• Time in Patent Office: Days
• US Class Current: 250/208.100
• CPC Class Codes: H04N 25/583 with different integration times
• CPC Class Codes: H04N 25/589 with different integration times, e.g. short and long exposures
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: H04N 3/155 Control of the image-sensor operation, e.g. image processing within the image-sensor

Abstract

A wide dynamic range imager with a dual integration, selective readout operating method that requires only one readout chain. First signals from a row of pixels are digitized and stored into a memory after a first integration period. A flag is set and stored in the memory for each pixel that reached a threshold value during the first integration period. Second signals from the row are read after a second shorter integration period. If the pixel'"'"'s corresponding flag bit was set, the second signal is stored (overwriting the first signal) and is subsequently used by processing circuitry to generate the appropriate pixel signal based on a full range signal and the second signal. Otherwise, the first signal is processed by the processing circuitry.

Claims

1. An imaging device comprising:

an array of pixels organized as a plurality of rows and columns;

a column readout circuit connected to the columns, said column readout circuit inputting from each column first signals associated with a first integration period and second signals associated with a second integration period, said column readout circuit outputting for each column a first digital value corresponding to the first signals and a second digital value corresponding to the second signals;

a first memory; and

a selector circuit connected to receive the first and second digital values, said selector storing for each column the first digital value and a corresponding indicator into the first memory, the indicator having a first state if the first digital value reached a predetermined threshold and a second state if the first digital value did not reach the predetermined threshold, wherein said selector stores into the first memory the second digital value for a column if the corresponding indicator is in the first state.

2. The imaging device of claim 1, wherein the first integration period is longer than the second integration period.

3. The imaging device of claim 2, wherein the first signals for a column comprise a reset signal obtained at a start of the first integration period and a pixel signal obtained during the first integration period.

4. The imaging device of claim 3, wherein the second signals for a column comprise a reset signal obtained at a start of the second integration period and a pixel signal obtained during the second integration period.

5. The imaging device of claim 1, wherein the second integration period is no longer than a horizontal line period.

6. The imaging device of claim 1, wherein the predetermined threshold comprises a voltage level corresponding to a pseudo saturation level of the pixels.

7. The imaging device of claim 1, further comprising:

a second memory, wherein the contents of the first memory are copied into the second memory; and

image processing circuitry, said image processing circuitry using the information from the second memory to generate and output synthesized pixel output signals for each readout pixel.

8. The imaging device of claim 7, wherein for each pixel having an indicator in the first state, the image processing circuit generates the synthesized output by adding the second digital value to a value corresponding to the difference between the predetermined threshold and a minimum threshold for the second digital value.

9. The imaging device of claim 7, wherein for each pixel having an indicator in the second state, the image processing circuit generates the synthesized output using the first digital value.

10. The imaging device of claim 7, wherein the image processing circuitry comprises:

a flag checker for checking and outputting the state of each indicator;

a synthesizer block for generating the synthesized output based on the state of the indicator; and

an image processing block for providing processing information to the synthesizer block.

11. The imaging device of claim 1, wherein the first and second digital values represent colored pixel signals and the predetermined threshold comprises a plurality of color signal thresholds, and wherein said selector determines a color associated with each first digital value and compares the first digital value to the respective color threshold in order to set the flag to one of the first and second states.

12. A CMOS imaging device comprising:

an array of pixels organized as a plurality of rows and columns;

means for inputting from each column first signals associated with a first integration period and second signals associated with a second integration period;

means for generating a first digital value corresponding to the first signals and a second digital value corresponding to the second signals;

means for storing each first digital value;

means for overwriting each first digital value with its corresponding second digital value when the first digital value has reached a predetermined threshold; and

means for generating a synthesized pixel output for each readout pixel based on the stored first and second digital values.

13. The imaging device of claim 12, wherein the first integration period is longer than the second integration period.

14. The imaging device of claim 12, wherein the first signals for a column comprise a reset signal obtained at a start of the first integration period and a pixel signal obtained during the first integration period.

15. The imaging device of claim 14, wherein the second signals for a column comprise a reset signal obtained at a start of the second integration period and a pixel signal obtained during the second integration period.

16. The imaging device of claim 12, wherein the second integration period is no longer than a horizontal line period.

17. The imaging device of claim 12, wherein the predetermined threshold comprises a voltage level corresponding to a pseudo saturation level of the pixels.

18. A processor system comprising:

an imaging device comprising;

an array of pixels organized as a plurality of rows and columns;

a column readout circuit connected to the columns, said column readout circuit inputting from each column first signals associated with a first integration period and second signals associated with a second integration period, said column readout circuit outputting for each column a first digital value corresponding to the first signals and a second digital value corresponding to the second signals;

a first memory; and

a selector circuit connected to receive the first and second digital values, said selector storing for each column the first digital value and a corresponding flag indicator into the first memory, the flag indicator having a first state if the first digital value reached a predetermined threshold and a second state if the first digital value did not reach the predetermined threshold, wherein said selector storing into the first memory the second digital value for a column if the corresponding flag indicator is in the first state.

19. The system of claim 18, wherein the first integration period is longer than the second integration period.

20. The system of claim 19, wherein the first signals for a column comprise a reset signal obtained at a start of the first integration period and a pixel signal obtained during the first integration period.

21. The system of claim 20, wherein the second signals for a column comprise a reset signal obtained at a start of the second integration period and a pixel signal obtained during the second integration period.

22. The system of claim 18, wherein the second integration period is no longer than a horizontal line period.

23. The system of claim 18, wherein the predetermined threshold comprises a voltage level corresponding to a pseudo saturation level of the pixels.

24. The system of claim 18, wherein said imaging device further comprises:

a second memory, wherein the contents of the first memory are copied into the second memory; and

image processing circuitry, said image processing circuitry using the information from the second memory to generate and output synthesized pixel output signals for each readout pixel.

25. The system of claim 24, wherein for each pixel having a flag indicator in the first state, the image processing circuit generates the synthesized output by adding the second digital value to a value corresponding to the difference between the predetermined threshold and a minimum threshold for the second digital value.

26. The system of claim 24, wherein for each pixel having a flag indicator in the second state, the image processing circuit generates the synthesized output using the first digital value.

27. The system of claim 24, wherein the image processing circuitry comprises:

a flag checker for checking and outputting the state of each flag indicator;

a synthesizer block for generating the synthesized output based on the state of the flag indicator; and

an image processing block for providing processing information to the synthesizer block.

28. The system of claim 18, wherein the first and second digital values represent colored pixel signals and the predetermined threshold comprises a plurality of color signal thresholds, and wherein said selector determines a color associated with each first digital value and compares the first digital value to the respective color threshold in order to set the flag to one of the first and second states.

29. A processor system comprising:

A CMOS imaging device comprising;

an array of pixels organized as a plurality of rows and columns;

means for inputting from each column first signals associated with a first integration period and second signals associated with a second integration period;

means for generating a first digital value corresponding to the first signals and a second digital value corresponding to the second signals;

means for storing each first digital value;

means for overwriting each first digital value with its corresponding second digital value when the first digital value has reached a predetermined threshold; and

means for generating a synthesized pixel output for each readout pixel based on the stored first and second digital values.

30. The system of claim 29, wherein the first integration period is longer than the second integration period.

31. The system of claim 29, wherein the first signals for a column comprise a reset signal obtained at a start of the first integration period and a pixel signal obtained during the first integration period.

32. The system of claim 30, wherein the second signals for a column comprise a reset signal obtained at a start of the second integration period and a pixel signal obtained during the second integration period.

33. The system of claim 29, wherein the second integration period is no longer than a horizontal line period.

34. The system of claim 29, wherein the predetermined threshold comprises a voltage level corresponding to a pseudo saturation level of the pixels.

35. A method of manufacturing an imaging device, said method comprising the acts of:

providing an array of pixels organized as a plurality of rows and columns;

providing a column readout circuit connected to the columns, wherein said column readout circuit inputs from each column first signals associated with a first integration period and second signals associated with a second integration period, and wherein said column readout circuit outputs for each column a first digital value corresponding to the first signals and a second digital value corresponding to the second signals;

providing a first memory; and

providing a selector circuit connected to receive the first and second digital values, wherein said selector stores for each column the first digital value and a corresponding indicator into the first memory, the indicator having a first state if the first digital value reached a predetermined threshold and a second state if the first digital value did not reach the predetermined threshold, wherein said selector stores into the first memory the second digital value for a column if the corresponding indicator is in the first state.

36. The method of claim 35, wherein said act of providing the column readout circuit comprises:

providing sample and hold circuitry connected to each column;

providing a differential amplifier connected to receive each column output from the sample and hold circuitry; and

providing an analog-to-digital converter connected to the output of the differential amplifier.

37. The method of claim 35, further comprising the acts of:

providing a second memory, wherein the contents of the first memory are copied into the second memory; and

providing image processing circuitry, wherein said image processing circuitry uses the information from the second memory to generate and output synthesized pixel output signals for each readout pixel.

38. The method of claim 37, wherein the act of providing the image processing circuitry comprises:

providing a flag checker for checking and outputting the state of each indicator;

providing a synthesizer block for generating the synthesized output based on the state of the indicator; and

providing an image processing block for providing processing information to the synthesizer block.

39. A method of operating an imaging device comprising the acts of:

starting a first integration period;

inputting from each column of pixels in a pixel array respective first signals associated with the first integration period;

converting the first signals into respective first digital values;

setting respective flags to a first state if their associated first digital value has exceeded a predetermined threshold and setting the flags to a second state if their associated first digital value has not exceeded the predetermined threshold;

storing the first digital values and the state of the flags into a first memory;

starting a second integration period;

inputting from each column second signals associated with the second integration period;

converting the second signals into respective second digital values;

storing the second digital values whose corresponding flags are set to the first state; and

generating a respective synthesized pixel output from the stored first and second values.

40. The method of claim 39, wherein the first integration period is longer than the second integration period.

41. The method of claim 39, wherein the first signals comprise a reset signal obtained at the start of the first integration period and a pixel signal obtained during the first integration period.

42. The method of claim 41, wherein the second signals comprise a reset signal obtained at the start of the first integration period and a pixel signal obtained during the second integration period.

43. The method of claim 39, wherein the second integration period is no longer than a horizontal line period.

44. The method of claim 39, wherein the predetermined threshold comprises a voltage level corresponding to a pseudo saturation level of the pixels.

45. The method of claim 39, further comprising the act of copying the first and second digital values and flags into a second memory prior to generating the synthesized pixel output.

46. The method of claim 39, wherein for each pixel having a flag bit in the first state, said generating act generates the synthesized output by adding the second digital value to a value corresponding to the difference between the predetermined threshold and a minimum threshold for the second digital value.

47. The method of claim 39, wherein for each pixel having a flag bit in the second state, said generating act generates the synthesized output using the first digital value.

48. The method of claim 39, wherein the first and second digital values represent colored pixel signals and the predetermined threshold comprises a plurality of color signal thresholds.