Novel conductive elements for thin film transistors used in a flat panel display

• US 20060011914A1
• Filed: 09/06/2005
• Published: 01/19/2006
• Est. Priority Date: 03/12/2003
• Status: Abandoned Application

• Current Assignee: Samsung Mobile Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Mobile Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Yoo, Kyung-Jin, Kim, Tae-Sung
• Application Number:
  US11/218,496
• Publication Number:
  US 20060011914A1
• Time in Patent Office: Days
• US Class Current: 257/59
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT

Abstract

A novel design for an electrode for a thin film transistor. The novel design allows for formation of a normal conductive channel between a source electrode and a drain electrode even after a heat treatment process, and a flat panel display including the thin film transistor. The thin film transistor includes a source electrode, a drain electrode, a gate electrode, and a semiconductor layer, wherein at least one of the source electrode, the drain electrode, and the gate electrode includes an aluminum alloy layer, and titanium layers are formed on both surfaces of the aluminum alloy layer. The electrodes are preferably absent any pure aluminum as pure aluminum can diffuse into the semiconductor layer causing a defect region and preventing a conductive channel from forming in the thin film transistor.

Claims

1. A thin film transistor, comprising a source electrode, a drain electrode, a gate electrode and a semiconductor layer, wherein at least one of the source electrode, the drain electrode, and the gate electrode comprises an aluminum alloy layer disposed between a pair of titanium layers.

2. The thin film transistor of claim 1, wherein the aluminum alloy layer comprises about 0.1 to 5 wt % of at least one element selected from a group consisting of silicon, copper, neodymium, platinum and nickel.

7. The thin film transistor of claim 1, each electrode being absent of pure aluminum.

23. The thin film transistor of claim 1, wherein the aluminum alloy layer comprises at least one element selected from a group consisting of silicon, copper, neodymium, platinum and nickel.

29. The thin film transistor of claim 1, wherein the aluminum alloy layer comprises 2 wt % of silicon.

30. The TFT of claim 1, wherein the aluminum alloy layer comprises 2 wt % of silicon.

3-6. -6. (canceled)

8. A flat panel display, comprising:

a substrate;

a first plurality of thin film transistors formed on a surface of the substrate, the first plurality of thin film transistors comprising first source electrodes, first drain electrodes, first gate electrodes, and semiconductor layers;

a plurality of first conductive lines electrically connected to the first source electrodes; and

a plurality of second conductive lines electrically connected to the first gate electrodes;

a second plurality of thin film transistors, wherein the first drain electrodes of the first plurality of thin film transistors are electrically connected to gate electrodes of the second plurality of thin film transistors, wherein at least one of the first source electrodes, the first drain electrodes, the first gate electrodes, the plurality of first conductive lines, and the plurality of second conductive lines comprises an aluminum alloy layer and a titanium layer arranged on at least one surface of the aluminum alloy layer.

9. The flat panel display of claim 8, wherein the aluminum alloy layer comprises about 0.1 to 5 wt % of at least one element selected from the group consisting of silicon, copper, neodymium, platinum and nickel.

24. The flat panel display of claim 8, wherein the aluminum alloy layer comprises at least one element selected from a group consisting of silicon, copper, neodymium, platinum and nickel.

27. The flat panel display of claim 8, wherein the aluminum alloy layer comprises 2 wt % of silicon.

10-13. -13. (canceled)

14. A TFT, comprising:

a source electrode, a gate electrode and a drain electrode; and

a semiconductor layer between the source electrode and the drain electrode.

wherein at least one of said source electrode and said drain electrode contains an aluminum alloy layer and absent pure aluminum.

15. The TFT of claim 14, wherein the aluminum alloy layer comprises about 0.1 to 5 wt % of at least one element selected from the group consisting of silicon, copper, neodymium, platinum and nickel.

17. The TFT of claim 14, said semiconductor layer being absent of aluminum after said TFT is subjected to a heat treatment of at least 300 degrees Celsius.

18. The TFT of claim 14, said semiconductor layer primarily comprising silicon and said semiconductive layer forming a conductive channel between said source electrode and said drain electrode upon application of a voltage to the gate electrode after said TFT is exposed to heat treatment of at least 300 degrees Celsius.

19. The TFT of claim 14, said source electrode and said drain electrode both comprise aluminum alloy and both being absent pure aluminum.

25. The TFT of claim 14, wherein the aluminum alloy layer comprises at least one element selected from a group consisting of silicon, copper, neodymium, platinum and nickel.

16. (canceled)

20. (canceled)

21. A process of manufacturing a flat panel display, the process comprising:

forming a first plurality of thin film transistors on a surface of a substrate, the first plurality of thin film transistors including first source electrodes, first drain electrodes, first gate electrodes, and semiconductor layers;

electrically connecting a plurality of first conductive lines to the first source electrodes;

electrically connecting a plurality of second conductive lines to the first gate electrodes; and

forming a second plurality of thin film transistors, and electrically connecting the first drain electrodes of the first plurality of thin film transistors to gate electrodes of the second plurality of thin film transistors;

wherein at least one of the first source electrodes, the first drain electrodes, the first gate electrodes, the plurality of first conductive lines, and the plurality of second conductive lines comprises an aluminum alloy layer and a titanium layer formed on at least one surface of the aluminum alloy layer.

22. The process of claim 21, further comprising forming the aluminum alloy layer to include about 0.1 to 5 wt % of at least one element selected from a group consisting of silicon, copper, neodymium, platinum and nickel.

26. The process of claim 21, further comprising forming the aluminum alloy layer to include at least one element selected from the group consisting of silicon, copper, neodymium, platinum and nickel.

28. The process of claim 21, further comprising forming the aluminum alloy layer to include 2 wt % of silicon.