Accumulation device with charge balance structure and method of forming the same

• US 20060011962A1
• Filed: 05/26/2005
• Published: 01/19/2006
• Est. Priority Date: 12/30/2003
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Kocon, Christopher Boguslaw
• Granted Patent: US 7,368,777 B2
• Time in Patent Office: Days
• US Class Current: 257/302
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/30655 comprising alternated and repeated etching and passivation steps, e.g. Bosch process
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/68363 used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/4952 the additional leads being a bump or a wire
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 : Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 : with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 : the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 : characterised by the surface lay-out
• CPC Class Codes: H01L 29/4933 : with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/495 : the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66734 : with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7802 : Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7804 : the other device being a pn-junction diode
• CPC Class Codes: H01L 29/7805 : in antiparallel, e.g. freewheel diode
• CPC Class Codes: H01L 29/7806 : the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7811 : with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7815 : with voltage or current sensing structure, e.g. emulator section, overcurrent sensing cell
• CPC Class Codes: H01L 29/7828 : without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
• CPC Class Codes: H01L 29/7831 : with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 29/7838 : without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01012 : Magnesium [Mg]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H02M 3/003 : Constructional details, e.g. physical layout, assembly, wiring or busbar connections
• CPC Class Codes: H02M 3/33592 : having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer
• CPC Class Codes: H02M 7/48 : using discharge tubes with control electrode or semiconductor devices with control electrode
• CPC Class Codes: Y02B 70/10 : Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

An accumulation-mode field effect transistor includes a plurality of gates and a semiconductor region having a channel region adjacent to but insulated from each of the plurality of gates. The semiconductor region further includes a conduction region wherein the channel regions and the conduction region are of a first conductivity type. The transistor further includes a drain terminal and a source terminal configured so that when the accumulation-mode field effect transistor is in the on state a current flows from the drain terminal to the source terminal through the conduction region and the channel regions. A number of charge balancing structures are integrated with the semiconductor region so as to extend parallel to the current flow. In a blocking state, the charge balancing structures influence an electric field in the conduction region so as to increase the blocking capability of the accumulation-mode field effect transistor.

Claims

1. An accumulation-mode field effect transistor comprising:

a plurality of gates;

a semiconductor region comprising a channel region adjacent to but insulated from each of the plurality of gates, and a conduction region, the channel regions and the conduction region being of a first conductivity type;

a drain terminal and a source terminal configured so that when the accumulation-mode field effect transistor is in the on state a current flows from the drain terminal to the source terminal through the conduction region and the channel regions;

a plurality of charge balancing structures each being integrated with the semiconductor region so as to extend parallel to the current flow, wherein in a blocking state the charge balancing structures influence an electric field in the conduction region so as to increase the blocking capability of the accumulation-mode field effect transistor.

13. The accumulation-mode field effect transistor of claim 1 wherein the plurality of charge balancing structures comprises a plurality of columns of silicon material of a second conductivity type opposite the first conductivity type, the conduction region and the plurality of columns of silicon material forming alternating columns of opposite conductivity type material extending between the source and drain terminals.

2-12. -12. (canceled)

14-66. -66. (canceled)

67. An accumulation-mode field effect transistor comprising:

a drain terminal and a source terminal;

a semiconductor region comprising;

a plurality of gate trenches extending into the semiconductor region from a top surface of the semiconductor region;

a channel region of a first conductivity type between each adjacent pair of the plurality of gate trenches;

a plurality of columns of conduction region of the first conductivity type extending directly below the plurality of gate trenches; and

a plurality of columns of silicon material of a second conductivity type opposite the first conductivity type extending directly below the channel regions,

wherein the plurality of columns of conduction region and the plurality of columns of silicon material abut each other to form alternating columns of opposite conductivity type regions extending between the source and drain terminals such that when the accumulation-mode field effect transistor is in the on state a current flows from the drain terminal to the source terminal through the plurality of columns of conduction region and the channel regions.

68. The accumulation-mode field effect transistor of claim 67 wherein the channel regions have a doping concentration lower than that of the plurality of columns of conduction region.

69. The accumulation-mode field effect transistor of claim 67 wherein the channel regions have the same doping concentration as the plurality of columns of conduction region.

70. The accumulation-mode field effect transistor of claim 67 wherein each of the channel regions comprises a plurality of regions of the second conductivity type laterally extending to abut the adjacent pair of gate trenches between which the plurality of regions of the second conductivity type are located.

71. The accumulation-mode field effect transistor of claim 67 wherein each of the channel regions comprises a first region of the first conductivity type laterally extending to abut the adjacent pair of trenches between which the first region is located, the first region having a doping concentration higher than that of the channel regions.

72. The accumulation-mode field effect transistor of claim 67 wherein each of the channel regions comprises first and second plurality of regions of the first conductivity type, the first plurality of regions abutting one of the adjacent pair of gate trenches between which the first plurality of regions are located, and the second plurality of regions abutting the other one of the adjacent pair of gate trenches between which the second plurality of regions are located, the first and second plurality of regions having a doping concentration higher than that of the channel regions.

73-102. -102. (canceled)