Termination for trench MIS device having implanted drain-drift region

• US 20060011976A1
• Filed: 09/21/2005
• Published: 01/19/2006
• Est. Priority Date: 03/26/2004
• Status: Active Grant

• Current Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Inventors: Chen, Qufei, Darwish, Mohamed N., Qi, Jainhai, Terrill, Kyle W.
• Granted Patent: US 7,795,675 B2
• Time in Patent Office: Days
• US Class Current: 257/341
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench MIS device is formed in a P-epitaxial layer that overlies an N-epitaxial layer and an N+ substrate. In one embodiment, the device includes an N-type drain-drift region that extends from the bottom of the trench to the N-epitaxial layer. Preferably, the drain-drift region is formed at least in part by fabricating spacers on the sidewalls of the trench and implanting an N-type dopant between the sidewall spacers and through the bottom of the trench. The drain-drift region can be doped more heavily than the conventional “drift region” that is formed in an N-epitaxial layer. Thus, the device has a low on-resistance. The device can be terminated by a plurality of polysilicon-filled termination trenches located near the edge of the die, with the polysilicon in each termination trench being connected to the mesa adjacent the termination trench. The polysilicon material in each termination trenches.

Claims

1. A semiconductor die containing an MIS device, said die comprising a first layer of a first conductivity type overlying a second layer of said first conductivity type, and a body region of a second conductivity type opposite to said first conductivity type overlying said first layer, said die further comprising:

a plurality of trenches, said trenches comprising active trenches and termination trenches, each of said trenches extending downward from a surface of said die through said body region and having a bottom located in said first layer;

a plurality of mesas located between said trenches and between one of said termination trenches and an edge of said die;

an active area comprising an MIS device, said MIS device comprising;

an active trench comprising a conductive gate material; and

a source region of said first conductivity type located adjacent said surface of said die and a sidewall of said active trench; and

a termination region comprising;

at least a first and a second termination trench, each of said termination trenches comprising a conductive material, said conductive material in each of said termination trenches being insulated from said body region and said first layer by a dielectric layer lining the sidewalls and bottom of said termination trench;

at least a first and a second metal layer above said surface of said die, said first metal layer being electrically connected to said conductive material in said first termination trench and a first portion of said body region in a first mesa between said first and second trenches, said second metal layer being electrically connected to said conductive material in said second termination trench and to a second portion of said body region in a second mesa on a side of said second termination trench opposite from said first mesa, wherein said conductive materials in said termination trenches are electrically isolated from each other and from said source region and said first layer.

2. The semiconductor die of claim 1 wherein each of said first and second mesas comprises a heavily-doped contact region of said second conductivity type at a surface of said die, said first and second metal layers being in contact with the heavily-doped contact regions in said first and second mesas, respectively.