Control of strain in device layers by selective relaxation

• US 20060011984A1
• Filed: 09/15/2005
• Published: 01/19/2006
• Est. Priority Date: 06/07/2002
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: AmberWave Systems Corporation
• Inventors: Currie, Matthew T.
• Granted Patent: US 7,307,273 B2
• Time in Patent Office: Days
• US Class Current: 257/352
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/76259 with separation/delamination along a porous layer
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/76275 Vertical isolation by bonding techniques
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/66242 Heterojunction transistors [HBT] with an active layer made of a group 13/15 material H01L29/66318
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/66787 with a gate at the side of the channel
• CPC Class Codes: H01L 29/66916 with a PN heterojunction gate
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78684 having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence
• CPC Class Codes: H01L 29/78687 with a multilayer structure or superlattice structure

Abstract

The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication. Strain in the strained semiconductors is controlled for improved device performance.

Claims

1. A method for forming a structure, the method comprising:

forming a strained semiconductor layer over a first substrate;

masking a strained portion of the strained semiconductor layer; and

selectively relaxing at least a portion of the strain in at least a portion of the strained semiconductor layer to define a relaxed portion of the strained semiconductor layer,

wherein the masked strained portion of the strained semiconductor layer remains strained.

2. The method of claim 1, wherein selectively relaxing at least a portion of the strain comprises performing a pre-amorphization implant by introducing a dose of isoelectronic ions into the strained semiconductor layer, the dose exceeding a critical dose for amorphization.

3. The method of claim 2, wherein a thickness of the amorphous region is more than 50% of a thickness of the strained semiconductor layer.

4. The method of claim 1, further comprising:

prior to selectively relaxing at least a portion of the strain, bonding the strained semiconductor layer to a dielectric layer disposed on a second substrate.

5. The method of claim 1, further comprising:

forming a first transistor including a first channel disposed in the relaxed portion and forming a second transistor including a second channel disposed in the strained portion.

6. The method of claim 5, further comprising:

forming a first strain-inducing stressor configured to induce a first type of strain in the first channel, and

forming a second strain-inducing stressor configured to induce a second type of strain in the second channel, wherein the first type of strain and the second type of strain are different.

7. The method of claim 6, wherein the first type of strain is tensile and the second type of strain is compressive.

8. The method of claim 6, wherein the first type of strain is compressive and the second type of strain is tensile.

9. A method for forming a structure, the method comprising:

providing a substrate comprising a strained semiconductor layer disposed over and contacting a dielectric layer disposed over a semiconductor substrate, the strained semiconductor layer having a first strain; and

forming a first transistor including

a channel disposed in a portion of the strained semiconductor layer, and

a strain-inducing stressor configured to induce a second strain in the channel.

10. The method of claim 9, wherein the strain-inducing stressor is at least one of (i) strain-inducing source and drain regions defined in respective recesses;

(ii) an overlayer disposed over a gate of the transistor;

(iii) a shallow-trench isolation region;

(iv) a gate electrode;

(v) metal-semiconductor alloy disposed on at least one of a gate, a source region and a drain region;

(vi) a sidewall spacer;

(vii) at least one void disposed below at least one of source region, a drain region, and a channel of the transistor; and

(viii) a package.

11. The method of claim 9, wherein the first transistor is selected from the group consisting of a MOSFET and a finFET.

12. The method of claim 9, further comprising:

forming a second transistor including a second channel disposed in a second portion of the strained semiconductor layer.

13. The method of claim 12, wherein the second transistor further includes a second strain-inducing stressor configured to induce a third strain in the second channel.

14. The method of claim 13, wherein a type of the second strain is different from a type of the third strain.

15. The method of claim 12, wherein the first transistor comprises an NMOS transistor and the second transistor comprises a PMOS transistor.

16. The method of claim 12, wherein the first channel is tensilely strained and the second channel is compressively strained.

17. The method of claim 12, wherein the first channel is strained and the second channel is relaxed.

18. A structure comprising:

a substrate comprising a substantially strained layer disposed over and contacting a dielectric layer disposed over a semiconductor substrate, the substantially strained layer having a first portion and a second portion;

a first transistor having

a first strained channel, the first channel disposed in the first portion of the substantially strained layer, and

a first strain-inducing stressor inducing only a portion of the strain in the first channel; and

a second transistor having

a second strained channel, the second channel disposed in the second portion of the substantially strained layer, and

at least one second strain-inducing stressor inducing substantially all of the strain in the second channel.

19. The structure of claim 18, wherein the first transistor comprises an NMOSFET, and the second transistor comprises a PMOSFET.

20. The structure of claim 18, wherein at least one of the first and second transistors comprises a finFET.

21. The structure of claim 18, wherein the type of strain induced by the first strain-inducing stressor is different from the type of strain induced by the at least one second strain-inducing stressor.

22. The structure of claim 21, wherein the type of strain induced by the first strain-inducing stressor is tensile and the type of strain induced by the at least one second strain-inducing stressor is compressive.

23. The structure of claim 21, wherein the type of strain induced by the first strain-inducing stressor is compressive and the type of strain induced by the at least one second strain-inducing stressor is tensile.

24. The structure of claim 18, wherein the first strain-inducing stressor is at least one of (i) strain-inducing source and drain regions defined in respective recesses;

(ii) an overlayer disposed over a gate of the first transistor;

(iii) a shallow-trench isolation region;

(iv) a gate electrode;

(v) metal-semiconductor alloy disposed on at least one of a gate, a source region, and a drain region;

(vi) a sidewall spacer of the first transistor;

(vii) at least one void disposed below at least one of source region, a drain region, and a channel of the first transistor; and

(viii) a package.

25. The structure of claim 18, wherein the at least one second strain-inducing stressor is at least one of (i) strain-inducing source and drain regions defined in respective recesses;

(ii) an overlayer disposed over a gate of the second transistor;

(iii) a shallow-trench isolation region;

(iv) a gate electrode;

(v) metal-semiconductor alloy disposed on at least one of a gate, a source region, and a drain region of the second transistor;

(vi) a sidewall spacer;

(vii) at least one void disposed below at least one of source region, a drain region, and a channel of the second transistor; and

(viii) a package.

26. The structure of claim 18, wherein the type of strain induced by the second strain-inducing stressor is different from a type of strain in the substantially strained layer.