Method for fabricating strained semiconductor structures and strained semiconductor structures formed thereby

• US 20060011990A1
• Filed: 07/15/2004
• Published: 01/19/2006
• Est. Priority Date: 07/15/2004
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Furukawa, Toshiharu, Holmes, Steven John, Koburger, Charles William III, Hakey, Mark Charles, Horak, David Vaclav
• Granted Patent: US 7,102,201 B2
• Time in Patent Office: Days
• US Class Current: 257/377
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/41725 Source or drain electrodes for field effect devices with monocrystalline semiconductor on source/drain region H01L29/0843
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Semiconductor fabrication methods and structures, devices and integrated circuits characterized by enhanced operating performance. The structures generally include first and second source/drain regions formed in a body of a semiconductor material and a channel region defined in the body between the first and second source/drain regions. Disposed in at least one of the first and second source/drain regions are a plurality of plugs each formed from a volume-expanded material that transfers compressive stress to the channel region. The compressively strained channel region may be useful, for example, for improving the operating performance of p-channel field effect transistors (PFET'"'"'s).

Claims

1. A semiconductor device structure comprising:

a body of a semiconductor material;

a conductive gate electrode;

a gate insulator separating the gate electrode from the body;

first and second source/drain regions formed flanking said gate electrode so as to define a side edge region in said body between said first and second source/drain regions and beneath said gate insulator; and

a plurality of plugs disposed in at least one of said first and second source/drain regions, said plugs being formed from a volume-expanded material that transfers compressive stress to said channel region.

2. The semiconductor structure of claim 1 wherein said plurality of plugs are formed from an insulating material.

3. The semiconductor structure of claim 1 wherein said body is silicon and said insulating material is silicon oxide.

4. The semiconductor structure of claim 1 wherein said compressive stress is effective to enhance carrier mobility in said channel region.

5. The semiconductor structure of claim 1 wherein adjacent plugs are separated by one of a plurality of gaps, and further comprising:

first and second contacts filling said plurality of gaps.

6. The semiconductor structure of claim 5 wherein each of said plurality of plugs is annular and includes a space filled with a portion of a corresponding one of said first and second contacts.

7. The semiconductor structure of claim 5 wherein said plurality of plugs are recessed and said first and second contacts overlie said plurality of plugs.

8. The semiconductor structure of claim 5 wherein said first and second contact layers are each formed of a silicide.

9. The semiconductor structure of claim 5 wherein said first and second contacts filling cover said plurality of plugs in a corresponding one of the first and second source/drain regions.

10. The semiconductor structure of claim 1 wherein each of said plurality of plugs has a maximum feature size of less than about 15 nanometers in diameter.

11. The semiconductor structure of claim 1 wherein said plurality of plugs extend to a depth in said body that is less than a depth of said first and second source/drain regions.

12. The semiconductor structure of claim 1 wherein said first and second source/drain regions include a p-type dopant species.

13. A method of fabricating a semiconductor structure in a body of a semiconductor material, the structure having first and second source/drain regions and a channel region between said first and second source/drain regions, comprising:

forming a pattern of open features in a masking layer overlying at least one of the first and second source/drain regions;

removing portions of the semiconductor material in at least one of the first and second source/drain regions exposed by the open features in the masking layer to define trenches; and

filling the trenches at least partially with a volume-expanded material effective to compressively stress the channel region.

14. The method of claim 13 wherein the body is silicon, and filling the trenches comprises:

oxidizing the semiconductor material surrounding the openings.

15. The method of claim 14 wherein the trenches are completely filled by the oxidized semiconductor material.

16. The method of claim 13 wherein each of the open features ranges in major dimension from about 2 nm to about 10 nm.

17. The method of claim 13 further comprising:

implanting a p-type dopant species into the first and second source/drain regions.

18. The method of claim 13 wherein forming the pattern of open features further comprises:

using nanolithography to form the pattern of open features in the masking layer.

19. The method of claim 18 wherein using nanolithography further comprises:

forming a layer of a self-assembled block copolymer covering the masking layer;

removing one component of the block copolymer selective to another component of the block copolymer to form a pattern of open features in the layer; and

etching the masking layer through the pattern of open features in the layer to form the pattern of open features in the masking layer.

20. The method of claim 13 further comprising:

forming first and second conductive contacts each over a corresponding one of the first and second source/drain regions after the trenches are filled with the volume-expanded material.

21. The method of claim 20 wherein forming the first and second conductive contacts further comprises:

performing a silicidation process to form the first and second conductive contacts.

22. The method of claim 20 wherein forming the first and second conductive contacts further comprises:

depositing a conductive material on the first and second source/drain regions to form the first and second conductive contacts.

23. The method of claim 20 further comprising:

recessing the volume-expanded material filling the trenches below the horizontal level of the first and second source/drain regions before the first and second conductive contacts are formed.

24. The method of claim 13 wherein filling the trenches further comprises;

partially filling the trenches with the volume-expanded material.