Semiconductor structure including silicide regions and method of making same

• US 20060011996A1
• Filed: 07/16/2004
• Published: 01/19/2006
• Est. Priority Date: 07/16/2004
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Cheng-Tung, Chang, Chih-Wei, Shue, Shau-Lin, Wu, Chii-Ming, Wang, Mei-Yun
• Granted Patent: US 7,396,767 B2
• Time in Patent Office: Days
• US Class Current: 257/412
• CPC Class Codes: H01L 21/28097 the final conductor layer next to the insulator being a metallic silicide
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66507 providing different silicide thicknesses on the gate and on source or drain

Abstract

A method of forming a silicided gate on a substrate having active regions, comprising the steps of: forming a first silicide in the active regions from a first material; and forming a second silicide in the gate from a second material, wherein the first silicide forms a barrier against the second material forming a silicide in the active regions during the second silicide forming step, wherein said second silicide is thicker than said first silicide.

Claims

1. A method of forming a silicided gate on a substrate having active regions, comprising the steps of:

forming a first silicide in the active regions from a first material; and

forming a second silicide in the gate from a second material, wherein said first silicide forms a barrier against said second material forming a silicide in said active regions during said second silicide forming step,

wherein said second silicide is thicker than said first silicide.

2. The method of claim 1,

wherein said first forming step comprises:

depositing said first material over said substrate and annealing to cause said first material to react with said active regions to form said first silicide; and

wherein said second forming step comprises;

depositing said second material over said substrate and annealing to cause said second material to react with said gate to form said second silicide, wherein said annealing of said second silicide forming step is performed at a temperature that substantially prevents said second material from reacting with said active regions.

3. The method of claim 2, wherein said temperature of said second silicide forming step is less than or equal to a temperature of said annealing of said first silicide forming step.

4. The method of claim 1, further comprising the steps of:

before said first silicide forming step, forming a shielding layer over said gate, whereby said shielding layer prevents said first material from reacting with the gate during said first silicide forming step.

5. The method of claim 4, wherein said shielding layer comprises SiN, SiON, SiC, SiCN or SiO₂.

6. The method of claim 4, further comprising the step of, after said first silicide forming step and before said second silicide forming step, removing said shielding layer over said gate.

7. The method of claim 6, wherein said removal step comprises etching said shielding layer with a solution comprising phosphoric acid or hydrogen fluoride.

8. The method of claim 2, wherein said first material comprises cobalt and said second material comprises nickel.

9. The method of claim 8, wherein said annealing of said first silicide forming step comprises an annealing at a temperature of at least about 650°

C., wherein said first silicide comprises CoSi₂.

10. The method of claim 9, wherein said annealing of said second silicide forming step comprises an annealing at a temperature between about 250-700°

C., wherein said second silicide comprises NiSi.

11. The method of claim 10, wherein said annealing of said second silicide forming step comprises annealing at a temperature between about 200-500°

C.

12. The method of claim 2, wherein said first and second materials comprise nickel.

13. The method of claim 12, wherein said annealing of said first silicide forming step comprises an annealing at a temperature between about 250-700°

C.

14. The method of claim 13, wherein said annealing of said second silicide forming step comprises an annealing at a temperature less than or equal to about the annealing temperature of said first silicide forming step.

15. The method of claim 1, wherein said second silicide forming step comprises fully siliciding said gate.

16. The method of claim 1, wherein said first silicide comprises a lowest resistivity phase of said first material and said second silicide comprises a lowest resistivity phase of said second material.

17. The method of claim 16, wherein said first and second materials comprise different materials.

18. An integrated circuit comprising a substrate having active regions formed therein and a gate formed thereon, wherein said active regions have a first silicide formed therein at a first annealing temperature, and said gate has a second silicide formed therein at a second annealing temperature less than or equal to said first annealing temperature, wherein said second silicide is thicker than said first silicide.

19. The integrated circuit of claim 18, wherein said first silicide comprises a lowest resitivity phase of a first material and said second silicide comprises a lowest resitivity phase of a second material.

20. The integrated circuit of claim 19, wherein said first and second materials comprises different materials.

21. The integrated circuit of claim 20, wherein the first material comprises cobalt and said second material comprises nickel.

22. The integrated circuit of claim 21 wherein said first silicide comprises CoSi₂ and said second silicide comprises NiSi.

23. The integrated circuit of claim 19, wherein the first and second materials comprise nickel.

24. The integrated circuit of claim 18, wherein said gate is fully silicided.

25. A method of forming a silicided gate on a substrate having active regions, comprising the step of:

(a) forming a shielding layer over said gate;

(b) after said forming step, depositing a first metal over said substrate;

(c) annealing to cause the first metal to react with the active regions to form a first silicide therein, whereby said shielding layer prevents said first metal from reacting with the gate during said annealing step;

(d) removing said shielding layer over said gate;

(e) depositing a second metal over said substrate; and

(f) annealing at a temperature at or below about an annealing temperature of step (c) to cause the second metal to react with the gate to form a second silicide in said gate,

wherein said first silicide forms a barrier against said second metal forming a silicide in said active regions during step (f), and

wherein said second silicide is formed to a thickness greater than said first silicide.

26. The method of claim 25, wherein said first silicide comprises a lowest resistivity phase of said first metal and said second silicide comprises a lowest resistivity phase of said second metal.

27. The method of claim 26, wherein said first and second metals comprise different materials.

28. The method of claim 27, wherein said first silicide comprises CoSi₂ and said second silicide comprises NiSi.

29. The method of claim 25, wherein said shielding layer comprises SiN, SiON, SiC, SiCN or SiO₂.

30. The method of claim 25, wherein said gate is fully silicided.

31. The method of claim 25, wherein said first and second metals comprise nickel and said first and second silicides comprise NiSi.

32. An integrated circuit comprising a substrate having active regions formed therein and a gate formed thereon, wherein said active regions have a first silicide formed therein from a first material, and said gate has a second silicide formed therein from a second material, wherein said second silicide is thicker than said first silicide and said first material is different than said second material.

33. The integrated circuit of claim 32, wherein said first silicide comprises a lowest resitivity phase of a first material and said second silicide comprises a lowest resitivity phase of a second material.

34. The integrated circuit of claim 32, wherein the first material comprises cobalt and said second material comprises nickel.

35. The integrated circuit of claim 34 wherein said first silicide comprises CoSi₂ and said second silicide comprises NiSi.

36. The integrated circuit of claim 35, wherein said gate is fully silicided.