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System and method for clock synchronization over packet-switched networks

  • US 20060013263A1
  • Filed: 07/19/2005
  • Published: 01/19/2006
  • Est. Priority Date: 07/19/2004
  • Status: Active Grant
First Claim
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1. A system for clock synchronization over packet-switched networks comprising:

  • a network;

    a first node selected from a group of nodes wherein said first node is coupled with said network and wherein said first node comprises;

    a packetizer;

    an error correction module;

    a time clock to time stamp a first packet and a second packet;

    a plurality of second nodes selected from said group of nodes wherein said plurality of second nodes are coupled with said network and wherein said plurality of second nodes comprises;

    a receiver time clock;

    a quality of service module comprising a de-jitter queue and a second error correction module;

    a clock recovery module coupled with said receiver time clock and said quality of service module and wherein said clock recovery module is used to generate a first difference between a first packet timestamp taken from said first packet and said receiver time clock and a second difference between a second packet timestamp taken from said second packet and said receiver time clock;

    said clock recovery module further comprising a shortest-delay offset generator;

    said shortest-delay offset generator comprising a fifo-buffer sliding window for holding said first difference and said second difference and a comparator and wherein said shortest-delay offset generator calculates an offset correction estimation of a fundamental network propagation delay using said first difference and said second difference;

    said clock recovery module configured to generate a recovered clock value from said receiver time clock and said offset correction estimation; and

    , said first node configured to transmit to said plurality of said second nodes.

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