System and method for clock synchronization over packet-switched networks
First Claim
1. A system for clock synchronization over packet-switched networks comprising:
- a network;
a first node selected from a group of nodes wherein said first node is coupled with said network and wherein said first node comprises;
a packetizer;
an error correction module;
a time clock to time stamp a first packet and a second packet;
a plurality of second nodes selected from said group of nodes wherein said plurality of second nodes are coupled with said network and wherein said plurality of second nodes comprises;
a receiver time clock;
a quality of service module comprising a de-jitter queue and a second error correction module;
a clock recovery module coupled with said receiver time clock and said quality of service module and wherein said clock recovery module is used to generate a first difference between a first packet timestamp taken from said first packet and said receiver time clock and a second difference between a second packet timestamp taken from said second packet and said receiver time clock;
said clock recovery module further comprising a shortest-delay offset generator;
said shortest-delay offset generator comprising a fifo-buffer sliding window for holding said first difference and said second difference and a comparator and wherein said shortest-delay offset generator calculates an offset correction estimation of a fundamental network propagation delay using said first difference and said second difference;
said clock recovery module configured to generate a recovered clock value from said receiver time clock and said offset correction estimation; and
, said first node configured to transmit to said plurality of said second nodes.
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Accused Products
Abstract
Embodiments of the invention enable the synchronization of clocks across packet switched networks, such as the Internet, sufficient to drive a jitter buffer and other quality-of-service related buffering. Packet time stamps referenced to a local clock create a phase offset signal. A shortest-delay offset generator uses a moving-window filter to select the samples of the phase offset signal having the shortest network propagation delay within the window. This shortest network propagation delay filter minimizes the effect of network jitter under the assumption that queuing delays account for most of the network jitter. The addition of this filtered phase offset signal to a free-running local clock creates a time reference that is synchronized to the remote clock at the source thus allowing for the transport of audio, video, and other time-sensitive real-time signals with minimal latency.
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Citations
20 Claims
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1. A system for clock synchronization over packet-switched networks comprising:
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a network;
a first node selected from a group of nodes wherein said first node is coupled with said network and wherein said first node comprises;
a packetizer;
an error correction module;
a time clock to time stamp a first packet and a second packet;
a plurality of second nodes selected from said group of nodes wherein said plurality of second nodes are coupled with said network and wherein said plurality of second nodes comprises;
a receiver time clock;
a quality of service module comprising a de-jitter queue and a second error correction module;
a clock recovery module coupled with said receiver time clock and said quality of service module and wherein said clock recovery module is used to generate a first difference between a first packet timestamp taken from said first packet and said receiver time clock and a second difference between a second packet timestamp taken from said second packet and said receiver time clock;
said clock recovery module further comprising a shortest-delay offset generator;
said shortest-delay offset generator comprising a fifo-buffer sliding window for holding said first difference and said second difference and a comparator and wherein said shortest-delay offset generator calculates an offset correction estimation of a fundamental network propagation delay using said first difference and said second difference;
said clock recovery module configured to generate a recovered clock value from said receiver time clock and said offset correction estimation; and
,said first node configured to transmit to said plurality of said second nodes. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method for clock synchronization over packet-switched networks comprising:
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packetizing data into a first packet in a first node selected from a group of nodes wherein said first node is coupled with a network;
packetizing data into a second packet in said first node;
time stamping said first packet in said first node;
time stamping said second packet in said first node;
transmitting said first packet and said second packet over said network;
providing software to a plurality of second nodes selected from said group of nodes wherein said plurality of second nodes are coupled with said network and wherein said plurality of second nodes are configured to generate a shortest delay offset wherein said software comprises the steps of;
recovering a clock by generating a first difference between a first packet timestamp taken from said first packet and a receiver time clock and a second difference between a second packet timestamp taken from said second packet and said receiver time clock;
said recovering said clock comprising utilizing a quality of service module comprising a de-jitter queue and a error correction module;
said recovering said clock comprising utilizing a shortest-delay offset generator comprising a fifo-buffer sliding window for holding said first difference and said second difference and a comparator;
said shortest-delay offset generator utilized in calculating an offset correction estimation of a fundamental network propagation delay using said first difference and said second difference;
generating a recovered clock value from said receiver time clock and said offset correction estimation. transmitting said first packet and said second packet to said plurality of said second nodes. - View Dependent Claims (12, 13, 14, 17)
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15. The method of claim 111 further comprising utilizing a ramp-rate limiter coupled with a comparator output.
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16. A system for clock synchronization over packet-switched networks comprising:
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means for packetizing data into a first packet in a first node selected from a group of nodes wherein said first node is coupled with a network;
means for packetizing data into a second packet in said first node;
means for time stamping said first packet in said first node;
means for time stamping said second packet in said first node;
means for transmitting said first packet and said second packet over said network;
means for providing software to a plurality of second nodes selected from said group of nodes wherein said plurality of second nodes are coupled with said network and wherein said plurality of second nodes are configured to generate a shortest delay offset wherein said software comprises the steps of;
means for recovering a clock by generating a first difference between a first packet timestamp taken from said first packet and a receiver time clock and a second difference between a second packet timestamp taken from said second packet and said receiver time clock;
said means for recovering said clock comprising utilizing a quality of service module comprising a de-jitter queue and a error correction module;
said means for recovering said clock comprising utilizing a shortest-delay offset generator comprising a fifo-buffer sliding window for holding said first difference and said second difference and a comparator;
said shortest-delay offset generator utilized in calculating an offset correction estimation of a fundamental network propagation delay using said first difference and said second difference;
means for generating a recovered clock value from said receiver time clock and said offset correction estimation. means for transmitting said first packet and said second packet to said plurality of said second nodes. - View Dependent Claims (18, 19, 20)
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Specification