Integrated circuit package having reduced interconnects

• US 20060014317A1
• Filed: 09/01/2005
• Published: 01/19/2006
• Est. Priority Date: 04/19/2002
• Status: Active Grant

• Current Assignee: Round Rock Research LLC
• Original Assignee: Round Rock Research LLC
• Inventors: Farnworth, Warren M., Brooks, Jerry M.
• Granted Patent: US 7,674,652 B2
• Time in Patent Office: Days
• US Class Current: 438/108
• CPC Class Codes: H01L 2224/4824 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06558 the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
• CPC Class Codes: H01L 2225/06565 the devices having the same size and there being no auxiliary carrier between the devices
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: Y02E 10/548 Amorphous silicon PV cells

Abstract

A technique for making an integrated circuit package. Specifically, a stacked memory device is provided with minimal interconnects. Memory die are stacked on top of each other and electrically coupled to a substrate. Thru vias are provided in the substrate and/or memory die to facilitate the electrical connects without necessitating a complex interconnect technology between each of the interfaces. Wire bonds are used to complete the circuit package.

Claims

1. A method of making an integrated circuit package comprising the acts of:

providing each of a substrate, a first die having a circuit side and a backside, and a second die having a circuit side and a backside and having connections extending through the second die;

coupling the backside of the first die to the substrate via a layer of at least one of a paste, epoxy, or film;

stacking the second die on the first die such that the backside of the second die is adjacent to the circuit side of the first die;

coupling the connections on the backside of the second die to second conductive pads on the circuit side of the first die; and

coupling the connections on the circuit side of the second die to first conductive pads on the substrate, such that the circuit side of the first die is electrically coupled to the substrate through the connections.

2. The method, as set forth in claim 1, wherein the first die is a memory die.

3. The method, as set forth in claim 2, wherein the second die is a memory die.

4. The method, as set forth in claim 1, wherein the act of coupling the backside of the first die to the substrate comprises the act of adhesively coupling the backside of the first die to the substrate with a non-conductive paste.

5. The method, as set forth in claim 1, wherein the act of coupling the backside of the first die to the substrate comprises the act of adhesively coupling the backside of the first die to the substrate with a non-conductive epoxy.

6. The method, as set forth in claim 1, wherein the act of coupling the backside of the first die to the substrate comprises the act of adhesively coupling the backside of the first die to the substrate with a film.

7. The method, as set forth in claim 1, wherein the act of coupling the connections on the backside of the second die comprises the act of coupling the connections on the backside of the second die to the first conductive pads on the circuit side of the first die via solder balls.

8. The method, as set forth in claim 1, wherein the act of coupling the connections on the circuit side of the second die comprises the act of coupling the connections on the circuit side of the second die to the second conductive pads on the substrate via bondwires.

9. The method, as set forth in claim 1, wherein each of the connections through the second die comprises:

a ball pad on the backside of the second die;

a bond pad on the circuit side of the second die; and

a conductive path electrically coupled between the ball pad and the bond pad.

10. A method of making an electronic device comprising the acts of:

providing each of a processor, substrate, a first die having a circuit side and a backside, and a second die having a circuit side and a backside and having connections extending through the second die;

coupling the backside of the first die to the substrate via a layer of at least one of a paste, epoxy, or film;

stacking the second die on the first die such that the backside of the second die is adjacent to the circuit side of the first die;

coupling the connections on the backside of the second die to second conductive pads on the circuit side of the first die;

coupling the connections on the circuit side of the second die to first conductive pads on the substrate, such that the circuit side of the first die is electrically coupled to the substrate through the connections; and

placing the processor in electrical communication with the second die.

11. The method, as set forth in claim 10, wherein the first die is a memory die.

12. The method, as set forth in claim 11, wherein the second die is a memory die.

13. The method, as set forth in claim 10, wherein the act of coupling the backside of the first die to the substrate comprises the act of adhesively coupling the backside of the first die to the substrate with a non-conductive paste.

14. The method, as set forth in claim 10, wherein the act of coupling the backside of the first die to the substrate comprises the act of adhesively coupling the backside of the first die to the substrate with a non-conductive epoxy.

15. The method, as set forth in claim 10, wherein the act of coupling the backside of the first die to the substrate comprises the act of adhesively coupling the backside of the first die to the substrate with a film.

16. The method, as set forth in claim 10, wherein the act of coupling the connections on the backside of the second die comprises the act of coupling the connections on the backside of the second die to the first conductive pads on the circuit side of the first die via solder balls.

17. The method, as set forth in claim 10, wherein the act of coupling the connections on the circuit side of the second die comprises the act of coupling the connections on the circuit side of the second die to the second conductive pads on the substrate via bondwires.

18. The method, as set forth in claim 10, wherein each of the connections through the second die comprises:

a ball pad on the backside of the second die;

a bond pad on the circuit side of the second die; and

a conductive path electrically coupled between the ball pad and the bond pad.

19. The method, as set forth in claim 10, wherein the electronic device is a computer.

20. The method, as set forth in claim 10, wherein the electronic device is a cellular telephone.