Floating-body DRAM in tri-gate technology

• US 20060014331A1
• Filed: 06/30/2004
• Published: 01/19/2006
• Est. Priority Date: 06/30/2004
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Paillet, Fabrice, Datta, Suman, Doyle, Brian, Khellah, Muhammad M., Keshavarzi, Ali, Ye, Yibin, Lu, Shih-Lien L., Somasekhar, Dinesh, Tang, Stephen H., De, Vivek K.
• Granted Patent: US 7,098,507 B2
• Time in Patent Office: Days
• US Class Current: 438/149
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/056 the transistor being a FinFET
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 12/36 the transistor being a FinFET

Abstract

A floating-body dynamic random access memory device may include a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer may be formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode may be formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. The gate electrode may only partially deplete a region of the semiconductor body, and the partially depleted region may be used as a storage node for logic states.

Claims

1. A partially depleted silicon-on-insulator transistor, comprising:

a silicon body formed on an insulating film, wherein said silicon body has a top surface, a first laterally opposite sidewall, and a second laterally opposite sidewall;

a gate dielectric formed on and around said silicon body;

a gate electrode formed on said gate dielectric on and around said silicon body; and

a pair of source/drain regions formed in said silicon body on opposite sides of said gate electrode, wherein said gate electrode has a gate length less than or equal to half of a width between laterally opposite sidewalls of said silicon body, and when said transistor is turned “

ON”

said silicon body between said source/drain regions is partially depleted to create a storage node.

2. The transistor of claim 1, wherein said storage node is a quasi-neutral floating-body.

3. The transistor of claim 1, wherein said gate length is less than about 60 nanometers.

4. The transistor of claim 1 wherein said gate length is less than or equal to the height of said silicon body on said insulating film.

5. The transistor of claim 1 wherein said silicon body is a single crystalline silicon film.

6. The transistor of claim 5 wherein said single crystalline silicon film is intrinsic silicon.

7. The transistor of claim 1, wherein said transistor has a gate length approximately equal to the distance between said first and second laterally opposite sidewalls of said silicon body.

8. The transistor of claim 1, wherein said transistor has a gate length approximately equal to the distance from said insulating film to the top surface of said silicon body.

9. The transistor of claim 1, wherein the distance between said laterally opposite sidewalls of said silicon body is approximately equal to the distance from said insulating substrate to the top surface of said silicon body.

10. The transistor of claim 1, wherein the distance between said laterally opposite sidewalls of said semiconductor is between approximately one-half and two times the thickness of said silicon body on said insulating surface.

11. The transistor of claim 1, further comprising:

a pair of sidewall spacers formed along laterally opposite sidewalls of said gate electrode.

12. The transistor of claim 1, wherein said pair of source/drain regions further comprises silicon formed on and around said silicon body.

13. The transistor of claim 12, wherein said silicon on said source/drain regions is epitaxial silicon.

14. A method of forming a partially-depleting, silicon-on-insulator transistor, comprising:

patterning a silicon film formed on an insulating substrate into a silicon body having a top surface opposite a bottom surface formed on said insulating film, and a first and second laterally opposite sidewalls;

forming a gate dielectric layer on said top surface of said silicon body and on said sidewalls of said silicon body;

depositing a gate material over said silicon body and over said insulating substrate;

patterning said gate material to form a gate electrode on said gate dielectric layer on said top surface of said silicon body and adjacent to said gate dielectric on said sidewalls of said silicon body, said gate electrode having laterally opposite sidewalls which run perpendicular to the laterally opposite sidewalls of said silicon body; and

forming a pair of source/drain regions in said silicon body on opposite sides of said laterally opposite sidewalls of said gate electrode, wherein said gate electrode has a gate length less than or equal to half of a width between laterally opposite sidewalls of said silicon body.

15. The method of claim 14, wherein said gate length is approximately equal to the thickness of said silicon body on said insulating substrate.

16. The method of claim 14, wherein said gate length is less than or equal to the thickness of said silicon body on said insulating film.

17. The method of claim 14, wherein said silicon film is single crystalline silicon.

18. The method of claim 17, wherein said single crystalline silicon film is intrinsic silicon.

19. The method of claim 14, further comprising:

forming a pair of sidewall spacers on opposite sides of laterally opposite sidewalls of said gate electrode; and

forming a silicon film on and around said silicon body and adjacent to said sidewall spacers.

20. The method of claim 14, further comprising:

forming a silicide on said silicon film formed on said silicon body.

21. The method of claim 14, further comprising:

forming said silicon film by a selective deposition process.

22. A floating-body, dynamic random access memory (FBDRAM) device, comprising:

a silicon body formed on an insulating film, wherein said silicon body has a top surface, a first laterally opposite sidewall, and a second laterally opposite sidewall;

a gate dielectric formed on and around said silicon body;

a gate electrode formed on said gate dielectric on and around said silicon body;

a pair of source/drain regions formed in said silicon body on opposite sides of said gate electrode; and

a storage node in a central region of said silicon body between said pair of source/drain regions, wherein said storage node is partially depleted to store a logic state.

23. The device of claim 22, wherein said storage node is a quasi-neutral floating-body.

24. The device of claim 22, wherein a write operation uses impact ionization to generate an excess body charge in said silicon body, wherein said excess body charge alters a threshold voltage of said pair of source/drain regions.

25. The device of claim 24, wherein the amount of excess body charge determines said logic state.

26. The device of claim 25, wherein said source/drain current is modulated to allow said logic state to be at least one of sensed or read.

27. The device of claim 22, wherein a read operation compares a source/drain current of said source/drain regions to a reference current to obtain said logic state.

28. The device of claim 22, wherein a write operation uses a forward biasing of a drain to body diode to discharge said silicon body.

29. The device of claim 22, wherein periodic refreshing of said device is performed to maintain said logic state.

30. The device of claim 22, wherein said device is organized in an array of FBDRAM devices with at least one pair of bit and word lines to select at least one of columns and rows.