Planarized and silicided trench contact

• US 20060014349A1
• Filed: 09/15/2005
• Published: 01/19/2006
• Est. Priority Date: 03/05/2003
• Status: Active Grant

• Current Assignee: Michael E. Cornell, Richard K. Williams, Wai Tien Chan
• Original Assignee: Michael E. Cornell, Richard K. Williams, Wai Tien Chan
• Inventors: Williams, Richard K., Chan, Wai Tien, Cornell, Michael E.
• Granted Patent: US 7,419,878 B2
• Time in Patent Office: Days
• US Class Current: 438/270
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4925 with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with only a vertical doping structure or vertical doping variation H01L29/4916
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/4941 with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Power MOSFETs and fabrication processes for power MOSFETs use a continuous conductive gate structure within trenches to avoid problems arising from device topology caused when a gate bus extends above a substrate surface. The gate bus trench and/or gate structures in the device trenches can contain a metal/silicide to reduce resistance, where polysilicon layers surround the metal/silicide to prevent metal atoms from penetrating the gate oxide in the device trenches. CMP process can remove excess polysilicon and metal and planarize the conductive gate structure and/or overlying insulating layers. The processes are compatible with processes forming self-aligned or conventional contacts in the active device region.

Claims

1. A fabrication process for a power MOSFET comprising:

forming a first trench in a substrate;

forming a second trench in the substrate;

doping a mesa in the substrate adjacent the first trench to form a vertical device including a source region, a channel region, and a drain region that are vertically aligned along a wall of the first trench;

forming a conductive gate structure that extends continuously from the first trench into the second trench, wherein the gate structure comprises a first portion that is in the first trench and acts as a gate of the vertical device, and a second portion that is in the second trench and forms a gate bus that including a metal/silicide region;

planarizing a structure including the substrate and the conductive gate structure in the first and second trenches; and

depositing a contact layer after planarizing the structure, wherein the contact layer includes a first region contacting the vertical device adjacent to the first trench and a second region overlying the second trench and contacting the gate bus.

2. The process of claim 1, further comprising forming an insulating layer overlying the conductive gate structure.

3. The process of claim 2, wherein the planarizing removes the insulating layer from above the mesa.

4. The process of claim 3, further comprising performing a contact etch that etches an opening through the insulating layer to expose a portion of the gate bus, the contact layer filling the opening and contacting the exposed portion of the gate bus in the second trench.

5. The fabrication process of claim 4, performing the contact etch forms a second opening through the insulating layer that exposes the mesa, the contact layer filling the second opening and contacting the vertical device.

6. The fabrication process of claim 2, further comprising:

forming a hard mask having openings that define boundaries of the first and second trenches, wherein the planarizing exposes a region of the hard mask overlying the mesa and leaves the regions of the insulating layer in the openings in the hard mask; and

removing the hard mask without removing the regions of the insulating layer left after the planarizing, wherein the contact layer contacts the mesa where the region of the hard mask was removed and the regions of the insulating layer separate the gate structure in the first trench from the contact layer.

7. The fabrication process of claim 1, further comprising forming a layer of a hard mask material on the substrate, wherein forming the second trench comprises patterning the hard mask material to form an opening over an area of the substrate corresponding to the second trench.

8. The fabrication process of claim 7, wherein forming the second trench comprises:

performing a LOCOS operation to oxidize the substrate in the area of the opening in the hard mask material; and

removing an oxide region formed during the LOCOS operation to leave the second trench in the substrate.

9. The fabrication process of claim 7, further comprising etching the substrate exposed through the opening in the hard mask material to thereby form the second trench.

10. The fabrication process of claim 7, wherein the second trench is wider than the first trench.

11. The process of claim 1, wherein planarizing comprises performing a chemical mechanical polishing (CMP) process on the structure.