Method for microfabricating structures using silicon-on-insulator material

• US 20060014358A1
• Filed: 09/20/2005
• Published: 01/19/2006
• Est. Priority Date: 01/02/2001
• Status: Active Grant

• Current Assignee: Charles Stark Draper Laboratory Incorporated
• Original Assignee: Charles Stark Draper Laboratory Incorporated
• Inventors: Borenstein, Jeffrey T., Sawyer, William D.
• Granted Patent: US 7,335,527 B2
• Time in Patent Office: Days
• US Class Current: 438/412
• CPC Class Codes: B81C 1/00182 Arrangements of deformable or non-deformable structures, e.g. membrane and cavity for use in a transducer
• CPC Class Codes: B81C 1/00579 Avoid charge built-up
• CPC Class Codes: B81C 2201/0191 Transfer of a layer from a carrier wafer to a device wafer
• CPC Class Codes: B81C 3/001 Bonding of two components

Abstract

The invention provides a general fabrication method for producing MicroElectroMechanical Systems (MEMS) and related devices using Silicon-On-Insulator (SOI) wafer. The method includes providing an SOI wafer that has (i) a handle layer, (ii) a dielectric layer, and (iii) a device layer, wherein a mesa etch has been made on the device layer of the SOI wafer, providing a substrate, wherein a pattern has been etched onto the substrate, bonding the SOI wafer and the substrate together, removing the handle layer of the SOI wafer, removing the dielectric layer of the SOI wafer, then performing a structural etch on the device layer of the SOI wafer to define the device.

Claims

1-23. -23. (canceled)

24. A method for producing micromachined devices, comprising the steps of:

(a) obtaining a Silicon-On-Insulator (SOI) wafer, which comprises

(i) a handle layer,

(ii) a dielectric layer, and

(iii) a device layer;

wherein a mesa etch has been made on the device layer of the SOI wafer, and a structural etch has been made in the device layer of the SOI wafer,

(b) obtaining a substrate, wherein a pattern has been formed onto the substrate;

(c) bonding the SOI wafer and the substrate together under a predetermined pressure less than atmosphere pressure;

(d) removing the handle layer of the SOI wafer; and

(e) removing the dielectric layer of the SOI wafer.

25. A method for producing micromachined devices, comprising the steps of:

(a) obtaining a Silicon-On-Insulator (SOI) wafer, which comprises

(i) a handle layer,

(ii) a dielectric layer, and

(iii) a device layer;

wherein a mesa etch has been made on the device layer of the SOI wafer, and a structural etch has been made in the device layer of the SOI wafer,

(b) obtaining a substrate, wherein a pattern has been formed onto the substrate;

(c) bonding the SOI wafer and the substrate together;

(d) removing the handle layer of the SOI wafer to a predetermined distance from the dielectric layer by a first etchant, wherein a relatively thin handle layer is left on the dielectric layer;

(e) removing the relatively thin handle layer by a second etchant; and

(f) removing the dielectric layer of the SOI wafer.

26. The method of claim 25, wherein said first etchant is a relatively fast etchant.

27. The method of claim 25, wherein said second etchant is a relatively slow etchant.

28. The method of claim 25, wherein said first etchant is potassium hydroxide (KOH).

29. The method of claim 25, wherein said second etchant is xenon difluoride (XeF₂).

30. The method of claim 25, wherein said second etchant is tetramethyl ammonium hydroxide (TMAH).

31. A structure with a substrate for etching with dry plasma etch having an element overlying and spaced apart from said substrate, comprising a metal layer deposited on said substrate, wherein said metal layer is substantially uniform under said element, wherein said metal layer includes one or more gaps in said metal layer, wherein said gaps are positioned other than under said element.