Programmable processor architecture

• US 20060015703A1
• Filed: 07/12/2005
• Published: 01/19/2006
• Est. Priority Date: 07/13/2004
• Status: Active Grant

• Current Assignee: Icelero LLC (Intellectual Ventures LLC)
• Original Assignee: Icelero LLC (Intellectual Ventures LLC)
• Inventors: Ramchandran, Amit, Hauser, John Reid Jr.
• Granted Patent: US 7,721,069 B2
• Time in Patent Office: Days
• US Class Current: 712/34
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 15/781 On-chip cache; Off-chip memory
• CPC Class Codes: G06F 15/7842 on one IC chip (single chip microcontrollers)
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 15/8053 Vector processors
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30038 using a mask
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/3828 with global bypass, e.g. between pipelines, between clusters
• CPC Class Codes: G06F 9/3877 using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3895 for complex operations, e.g. multidimensional or interleaved address generators, macros

Abstract

One embodiment of the present includes a heterogenous, high-performance, scalable processor having at least one W-type sub-processor capable of processing W bits in parallel, W being an integer value, at least one N-type sub-processor capable of processing N bits in parallel, N being an integer value wherein and smaller than W by a factor of two. The processor further includes a shared bus coupling the at least one W-type sub-processor and at least one N-type sub-processor and memory shared coupled to the at least one W-type sub-processor and the at least one N-type sub-processor, wherein the W-type sub-processor rearranges memory to accommodate execution of applications allowing for fast operations.

Claims

1. A heterogenous, high-performance, scalable processor comprising:

at least one W-type sub-processor capable of processing W bits, or more, in parallel, W being an integer value;

at least one N-type sub-processor capable of processing N bits in parallel, N being an integer value wherein and smaller than W;

Shared bus coupling the at least one W-type sub-processor and at least one N-type sub-processor; and

memory shared coupled to the at least one W-type sub-processor and the at least one N-type sub-processor,

wherein the W-type sub-processor rearranges bytes in transit to or from memory to accommodate execution of applications allowing for fast operations;

2. A heterogenous, high-performance, scalable processor, as recited in claim 1, wherein the processor is scalable.

3. A heterogenous, high-performance, scalable processor, as recited in claim 1, wherein two of at least one W-type sub-processors and two of the at least one N-type sub-processors.

4. A heterogenous, high-performance, scalable processor, as recited in claim 2, wherein the at least one W-type sub-processor and the at least N-type sub-processor execute programs for multimedia applications.

5. A heterogenous, high-performance, scalable processor, as recited in claim 4, wherein each of the at least one W-type sub-processors including a plurality of macro function units.

6. A heterogenous, high-performance, scalable processor, as recited in claim 5, wherein the plurality of macro function units includes a load store block for generating memory addresses for use by other of the plurality of the macro function units.

7. A heterogenous, high-performance, scalable processor, as recited in claim 6, wherein the plurality of macro function units includes a scalar arithmetic logic unit (ALU) and multiply accumulate block coupled to the load store block performing scalar arithmetic and logic and multiply operations on data received from the load store block.

8. A heterogenous, high-performance, scalable processor, as recited in claim 7, wherein the plurality of macro function units includes a vector X block coupled to the load store block and the scalar ALU and multiply accumulate block performing vector operations on data from the load store block, the vector X block generating vector data.

9. A heterogenous, high-performance, scalable processor, as recited in claim 8, wherein the plurality of macro function units includes a vector ALU and multiply accumulate block coupled to the scalar ALU and multiply accumulate block and the vector X block for performing vector ALU and multiply accumulate operations on vector data received from the vector X block.

10. A heterogenous, high-performance, scalable processor, as recited in claim 2, wherein the at least one N-type sub-processor includes a store unit block, an macro function blocks and a load unit block, the macro function blocks coupled to a load unit block and further coupled to a macro function bus for coupling the macro function blocks to the store block.

11. A heterogenous, high-performance, scalable processor, as recited in claim 10, wherein the at least one N-type sub-processor includes a data path unit (DPU) block and a controller, sequencer and data address generator (DAG) block shared by the at least one of the W-type of sub-processors.

12. A heterogenous, high-performance, scalable processor, as recited in claim 10, wherein the macro function blocks includes a Galois field multiply accumulate (MAC) block, coupled to the macro function bus and the load unit block 1306 and for performing Galois field operations.

13. A heterogenous, high-performance, scalable processor, as recited in claim 12, wherein the macro function blocks includes a special ALU, coupled to the load unit block and the a load unit block, for performing special ALU operations.

14. A heterogenous, high-performance, scalable processor, as recited in claim 13, wherein the macro function blocks includes a puncturing/depuncturing block coupled to the load unit block and the a load unit block and for performing puncturing/depuncturing operations.

15. A heterogenous, high-performance, scalable processor, as recited in claim 14, wherein the macro function blocks includes an interleaver block coupled to the load unit block and the a load unit block and for performing interleaving operations.

16. A heterogenous, high-performance, scalable processor, as recited in claim 15, wherein the macro function blocks includes a viterbi block coupled to the store unit block and the interleaver block and for performing viterbi operations.

17. A heterogenous, high-performance, scalable processor, as recited in claim 16, wherein the macro function blocks includes a combiner block coupled to the load unit block and the a load unit block and for performing combining operations.

18. A heterogenous, high-performance, scalable processor, as recited in claim 16, wherein the at least one N-type of sub-processors includes an X unit block coupled between the store unit block and the load unit block.

19. A heterogenous, high-performance, scalable processor, as recited in claim 16, including a shared register coupled between the at least one W-type sub-processor and the at least one N-type sub-processor for direct communication therebetween.

20. A method of processing information comprising:

heterogenous, high-performance, scalable processor comprising;

processing data using at least one W-type sub-processor capable of processing W bits in parallel, W being an integer value;

simultaneously processing data using at least one N-type sub-processor capable of processing N bits in parallel, N being an integer value wherein and smaller than W by a factor of two; and

causing fast execution of multimedia applications while maitaining low power consumption and ease of programmability.