Specifying data timeliness requirement and trap enabling on instruction operands of a processor

• US 20060015780A1
• Filed: 06/29/2005
• Published: 01/19/2006
• Est. Priority Date: 10/25/1995
• Status: Abandoned Application

• Current Assignee: CityU Research Limited
• Original Assignee: CityU Research Limited
• Inventors: Fong, Anthony S.
• Application Number:
  US11/172,370
• Publication Number:
  US 20060015780A1
• Time in Patent Office: Days
• US Class Current: 714/51
• CPC Class Codes: G06F 9/383 Operand prefetching cache prefetching G06F12/0862

Abstract

A computer has its programs in instructions and operand descriptors to specify the operands of the instructions. Apparatus for specifying data timeliness requirements of individual pieces of data pointed by the instruction operands is described hereby. The data timeliness requirements range from the local memory (the memory in the computing system processing the instructions), to the need to have the most updated copy of the piece of data in a system through the network (external memory), to any copy of the piece of data from external memory in a system through network. In a computer system wherein data items (operands) are represented by operand descriptors that can comprise object numbers, addresses, data types and sizes, vector information and other relevant information concerning the operands, with two bits to identify if the timeliness requirement of data of the operand, and one-bit flag of trap enabling of the corresponding operand, to enable a trap when the operand is encountered during processing of the instruction. The trap will further divert various handlers to service the trap according to the codes or flags set in the Processor Status Register or Processor Control Register in the processor.

Claims

1. In a computer system, including memory for storing instructions and operands, a central processor able to fetch and decode instructions, operand descriptor indexes, operand descriptors, and memory for storing an operand descriptors, a method for specifying data timeliness requirements on individual operands comprising:

in the central processor, specifying the data timeliness requirements of individual operands using said operand descriptors;

wherein said specifying is performed by setting or resetting the data timeliness requirement in an individual operand'"'"'s respective operand descriptor;

2. The method of claim 1 further comprising:

in the central processor, validating the data timeliness requirements of individual operands stored in said memory for storing operand descriptors against a memory operation requested by a process on the operand, and if said validating fails or if the required network-memory addresses for the data are not available, it will issue an exception to the operating system which will terminate said process;

3. The method of claim 1 further comprising:

in the central processor, the data timeliness requirements of individual operands stored in said memory for storing operand descriptors against a memory operation requested by a process on the operand, and the data timeliness requirements of individual operands are represented by two-bit codes, with individual unique codes to represent

a. data is to be in the local memory of the system processing the process;

b. data is to be from the external memory (memory of a system through networking of systems excluding the system that is processing the process, and the most updated copy is required;

c. data is to be from the external memory (memory of a system through networking of systems excluding the system that is processing the process, and the most updated copy is not required; and

4. The method of claim 1 further comprising:

in the central processor, the data timeliness requirements of individual operands stored in said memory for storing operand descriptors against a memory operation requested by a process on the operand, and the data timeliness requirements of individual operands are represented by two-bit codes, with individual unique codes to represent that the piece of data is to be from external memory, and the most dated copy is required, in that case, a table consisting of entries of network-memory addresses is required;

5. The method of claim 1 further comprising:

in the central processor, the data timeliness requirements of individual operands stored in said memory for storing operand descriptors against a memory operation requested by a process on the operand, and the data timeliness requirements of individual operands are represented by two-bit codes, with individual unique codes to represent that the piece of data is to be from external memory, and the most dated copy is required, in that case, a table consisting of entries of network-memory addresses is required, and if in a case of external memory such table is not available or invalid, an exception occurs, the process will be terminated and control flow will be passed to the operating system.

6. The method of claim 1 further comprising:

in the operand descriptor memory, storing the data timeliness requirements of individual operands through the operand descriptors.

7. The method of claim 1 further comprising:

in the central processor, validating the data timeliness requirements of a set of individual operand descriptors through a pre-determined allowable addresses for the individual operands established when a program is initiated.

12. The method of claim 1 wherein said computer system is a high-level instruction set computer system.

13. The method of claim 1 wherein said data timeliness requirement is specified and to be complied for an individual operand for the local memory/storage in the system which is processing the instruction containing the operand.

14. The method of claim 1 wherein said data timeliness requirement is specified and to be complied for an individual operand for external memory/storage in a system on the network which is not the system processing the instruction containing the operand, according to the data timeliness requirement of the operand descriptor to be the most updated or not.

15. The method of claim 1 wherein said data timeliness requirement is specified and to be complied for an individual operand for external memory/storage in a system on the network which is not the system processing the instruction containing the operand, with the data timeliness of to be the most updated. The network-memory addresses are needed to locate such copies of the data.

16. The method of claim 1 wherein said data timeliness requirement is specified and to be complied for an individual operand for external memory/storage in a system on the network which is not the system processing the instruction containing the operand, with the data timeliness of to be the most updated. The network-memory/storage addresses are needed to locate such copies of the data, but they are either unavailable or invalid. In these cases, an exception is activated, control flow will be passed to the operating system and the process will be terminated.

8. In a computer system, including memory for storing instructions and operands, a central processor able to fetch and decode instructions, operand descriptor indexes, operand descriptors, and memory for storing an operand descriptors, a method for specifying the trap enabling on individual operands comprising:

in the central processor, specifying the trap enabling of individual operands using said operand descriptors;

wherein said specifying is performed by setting or resetting the trap enabling in an individual operand'"'"'s respective operand descriptor;

9. The method of claim 8 further comprising:

in the operand cache, if the trap enabling is set, a trap will occur when the operand is encountered during processing of the instruction that contains the operand, and the control flow will be passed to a trap handler;

10. The method of claim 8 further comprising:

in the operand cache, if the trap enabling is set, a trap will occur when the operand is encountered during processing of the instruction that contains the operand, and the control flow will be passed to a trap handler, where control codes flags in the Processor Status Register or Processor Control Register will be examined, and control flow will be passed to individual sub-trap handlers which consist of single-steps, breakpoints, tracing on instruction addresses of a process being processed, trapping on requests of READ, WRITE, and EXECUTE memory operations, where EXECUTE is the fetching of instruction to be executed;

11. The method of claim 8 further comprising:

in the operand cache, if the trap enabling is set, a trap will occur when the operand is encountered during processing of the instruction that contains the operand, and the control flow will be passed to a trap handler, where control codes flags in the Processor Status Register or Processor Control Register will be examined, and control flow will be passed to individual sub-trap handlers which consist of single-steps, breakpoints, tracing on instruction addresses of a process being processed, trapping on requests of READ, WRITE, and EXECUTE memory operations, where EXECUTE is the fetching of instruction to be executed, for the corresponding operands, together with tracing, statistics updates (to increment the READ, WRITE, EXECUTE operation counts in the corresponding counters). These counters may be registers and handled by hardware logic, or memory locations and handled by software;