Test apparatus for mixed-signal semiconductor device

• US 20060015785A1
• Filed: 01/20/2005
• Published: 01/19/2006
• Est. Priority Date: 07/15/2004
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Chun, Byoung-Ok
• Granted Patent: US 7,472,321 B2
• Time in Patent Office: Days
• US Class Current: 714/724
• CPC Class Codes: G01R 31/3167 Testing of combined analog and digital circuits testing ADC's H03M1/1071
• CPC Class Codes: G01R 31/31924 Voltage or current aspects, e.g. driver, receiver

Abstract

A test apparatus for a mixed-signal semiconductor device that includes a plurality of event tester modules including analog and digital signal tester boards, a test head for event tester modules, a performance board including a socket for a DUT, a test fixture including a connection means, an option circuit for when the DUT is a mixed-signal integrated circuit including an analog and digital function blocks, a tester controller controlling the overall operation, and a switching parallel connection circuit sequentially connecting a single event tester board with a plurality of the DUTs. The event tester board and the DUTs are connected by a group unit. The number of parallel test is increased by an improved tester board or an improved performance board without the use of an extra event tester board for an analog signal test.

Claims

1. A test apparatus for testing a plurality of mixed-signal semiconductor devices under test (DUTs), said test apparatus comprising:

a plurality of event tester board modules including analog signal tester boards and digital signal tester boards;

a test head receiving the event tester modules;

a performance board that includes a socket for a DUT;

a test fixture including connection means, the connection means electrically connecting the performance board and the event tester module to the DUT and the event tester board;

an option circuit connected to the DUT when the DUT is a mixed-signal integrated circuit including an analog function block and a digital function block;

a tester controller for controlling the overall operation related to test; and

a switching parallel connection circuit for sequentially connecting each event tester board module with a plurality of the DUTs.

2. The test apparatus of claim 1, wherein the switching parallel connection circuit is in the performance board.

3. The test apparatus of claim 1, wherein the performance board includes an offset supply circuit.

4. The test apparatus of claim 3, wherein the offset supply circuit includes an offset adjustment circuit and a direct path, the offset adjustment circuit having, a low frequency signal source, a DC level source, a first OP amplifier and a second OP amplifier, the first OP amplifier using the low frequency signal source and the DC level as inputs and the second OP amplifier using the input of the first OP amplifier as one input and an output of the second OP amplifier as the other input, the direct path directly connecting the low frequency signal source and an output of the performance board.

5. The test apparatus of claim 1, wherein the event tester boards include event tester boards having a low frequency signal source function and event tester boards having a low frequency signal digitizer function.

6. The test apparatus of claim 1, wherein the event tester boards having the digitizer function are connected to the input and output of the DUT and the test controller calculates the phase difference between an input signal phase and an output signal phase by the measured value.

7. The test apparatus of claim 1, wherein the event tester boards having analog source/digitizer function are four, each event tester board is connected to two DUTs, and the DUTs are tested four two times by the switching operation of the switching parallel connection circuit.

8. The test apparatus of claim 1, wherein the test apparatus for the mixed-signal semiconductor device is a test apparatus for a SOC semiconductor device.

9. A test apparatus for testing a plurality of mixed-signal semiconductor devices under test (DUTs), said test apparatus comprising:

a plurality of event tester board modules including analog signal tester boards and digital signal tester boards;

a performance board that includes a plurality of socket for DUTs;

a test fixture including connection means, the connection means electrically connecting the performance board and the event tester module to the DUT and the event tester board;

an option circuit connected to the DUT when the DUT is a mixed-signal integrated circuit including an analog function block and a digital function block; and

a tester controller for controlling the overall operation of said tester.

10. The test apparatus of claim 9, wherein a switching parallel connection circuit for sequentially connecting each event tester board module with a plurality of the DUTs.

11. The test apparatus of claim 9, wherein the switching parallel connection circuit is part of said performance board.

12. The test apparatus of claim 9, wherein the performance board includes an offset supply circuit.

13. The test apparatus of claim 12, wherein said offset supply circuit includes an offset adjustment circuit and a direct path, the offset adjustment circuit having, a low frequency signal source, a DC level source, a first OP amplifier and a second OP amplifier, the first OP amplifier using the low frequency signal source and the DC level as inputs and the second OP amplifier using the input of the first OP amplifier as one input and an output of the second OP amplifier as the other input, the direct path directly connecting the low frequency signal source and an output of the performance board.

14. A test apparatus for testing a plurality of mixed-signal semiconductor devices under test (DUTs), said test apparatus comprising:

a plurality event tester board module means including a plurality of means for testing analog signals and a plurality of means for testing digital signals;

a performance board that includes a plurality of socket for DUTs;

a fixture means for electrically connecting the performance board and the event tester means to the DUT and the event tester board;

an option circuit connected to the DUT when the DUT is a mixed-signal integrated circuit including an analog function block and a digital function block;

parallel switching means for sequentially connecting each event tester board module with a plurality of the DUTs and

a tester controller for controlling the overall operation of said tester.

15. The test apparatus of claim 14, wherein the performance board includes an offset supply circuit, said offset supply circuit including an offset adjustment circuit and a direct path, the offset adjustment circuit having, a low frequency signal source, a DC level source, a first OP amplifier and a second OP amplifier, the first OP amplifier using the low frequency signal source and the DC level as inputs and the second OP amplifier using the input of the first OP amplifier as one input and an output of the second OP amplifier as the other input, the direct path directly connecting the low frequency signal source and an output of the performance board.