Semiconductor device with a high-k gate dielectric and a metal gate electrode

• US 20060017098A1
• Filed: 07/20/2004
• Published: 01/26/2006
• Est. Priority Date: 07/20/2004
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Chau, Robert S., Doczy, Mark L., Kavalieros, Jack, Brask, Justin K., Metz, Matthew V., Datta, Suman
• Granted Patent: US 7,148,548 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

A semiconductor device is described that comprises a gate dielectric and a metal gate electrode that comprises an aluminide.

Claims

1. A semiconductor device comprising:

a gate dielectric; and

a metal gate electrode, which is formed on the gate dielectric, that comprises an aluminide.

2. The semiconductor device of claim 1 wherein the gate dielectric comprises a high-k gate dielectric and the metal gate electrode comprises an aluminide with the composition M_xAl_y in which M is a transition metal.

3. The semiconductor device of claim 2 wherein the high-k gate dielectric comprises a material that is selected from the group consisting of hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

4. The semiconductor device of claim 2 wherein M comprises an element that is selected from the group consisting of zirconium, tungsten, tantalum, hafnium, and titanium.

5. The semiconductor device of claim 1 wherein the metal gate electrode has a workfunction that is less than about 4.3 eV.

6. The semiconductor device of claim 1 wherein the metal gate electrode is thermally stable at 400°

C.

7. A semiconductor device comprising:

a high-k gate dielectric; and

an NMOS metal gate electrode that comprises an aluminide with the composition M_xAl_y in which M is a transition metal.

8. The semiconductor device of claim 7 wherein:

the high-k gate dielectric comprises a material that is selected from the group consisting of hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate; and

M comprises an element that is selected from the group consisting of zirconium, tungsten, tantalum, hafnium, and titanium.

9. The semiconductor device of claim 7 wherein the NMOS metal gate electrode has a workfunction that is between about 3.9 eV and about 4.3 eV, and is thermally stable at 400°

C.

10. The semiconductor device of claim 7 wherein the NMOS metal gate electrode further comprises a fill metal that is formed on the aluminide.

11. The semiconductor device of claim 10 wherein the fill metal is selected from the group consisting of titanium nitride, tungsten, titanium, aluminum, tantalum, tantalum nitride, cobalt, copper, and nickel.

12. A CMOS semiconductor device comprising:

a high-k gate dielectric;

an NMOS metal gate electrode that comprises an aluminide with the composition M_xAl_y in which M is a transition metal; and

a PMOS metal gate electrode that does not comprise an aluminide.

13. The CMOS semiconductor device of claim 12 wherein:

the high-k gate dielectric comprises a material that is selected from the group consisting of hafnium oxide, zirconium oxide, and aluminum oxide;

M comprises an element that is selected from the group consisting of zirconium, tungsten, tantalum, hafnium, and titanium; and

the PMOS metal gate electrode comprises a material that is selected from the group consisting of ruthenium, palladium, platinum, cobalt, nickel, and a conductive metal oxide.

14. The CMOS semiconductor device of claim 12 wherein the NMOS metal gate electrode has a workfunction that is between about 3.9 eV and about 4.3 eV, and the PMOS metal gate electrode has a workfunction that is between about 4.9 eV and about 5.2 eV.

15. The CMOS semiconductor device of claim 12 wherein the aluminide has the composition M_xAl_y in which M is a transition metal, x is between 1 and 4 and y is between 1 and 4.

16. The CMOS semiconductor device of claim 15 wherein the aluminide is selected from the group consisting of ZrAl, ZrAl₂, ZrAl₃, WAl₄, TaAl, HfAl, TiAl, TiAl₂, TiAl₃, and Ti₃Al.

17. The CMOS semiconductor device of claim 12 wherein the NMOS metal gate electrode further comprises a fill metal that is formed on the aluminide.

18. The CMOS semiconductor device of claim 17 wherein the fill metal is selected from the group consisting of titanium nitride, tungsten, titanium, aluminum, tantalum, tantalum nitride, cobalt, copper, and nickel.

19. The CMOS semiconductor device of claim 12 wherein:

the high-k gate dielectric is formed using an atomic layer chemical vapor deposition process and is between about 5 angstroms and about 40 angstroms thick, and

the aluminide is between about 100 angstroms and about 300 angstroms thick.

20. The CMOS semiconductor device of claim 12 wherein both the NMOS metal gate electrode and the PMOS metal gate electrode are thermally stable at 400°

C.