Dynamic deep depletion field effect transistor

• US 20060017100A1
• Filed: 07/14/2005
• Published: 01/26/2006
• Est. Priority Date: 07/14/2004
• Status: Active Grant

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Li, Xin, Bol, Igor
• Granted Patent: US 7,462,908 B2
• Time in Patent Office: Days
• US Class Current: 257/331
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs

Abstract

A vertical conduction trench FET has a plurality of trenches containing conductive polysilicon gates. The mesas between the trenches have a source diffusion region connected to a common source electrode. The trenches are spaced so that the depletion regions induced by the trench gate will overlap to pinch off conduction through the mesa to turn off the device. The gate potential is pulsed. The polysilicon in the trenches may be separated into two insulated portions. The pulses may be applied simultaneously or sequentially to the polysilicon gates.

Claims

1. A semiconductor switching device comprising a semiconductor die of one conductivity type having a plurality of equally spaced trenches, spaced by mesa regions;

a gate insulation lining at least a portion of the walls of said trenches;

a conductive polysilicon mass deposed within said trenches for a height Wo from the bottom of said trench, a source contact disposed atop said die and in contact with said source region and insulated from said conductive polysilicon masses;

said mesas having a given width;

said polysilicon masses being connected to a source of gate to source bias for turning off said device at a given turn off-voltage;

said polysilicon masses producing depletion regions in the mesas adjacent said trench walls which depletion regions overlap one another to deplete said mesas and turn off the conduction channel between said source and drain electrodes when said turn off-voltage is applied to said polysilicon masses said source of gate to source bias being pulse voltage source.

2. The device of claim 1, wherein said mesa regions have a doping level of about 2E16/cm² and wherein said gate pulse creates said depletion regions in the order of 10s of milliseconds after the application of a pulse.

3. The device of claim 1, wherein said mesas have a width that is optimized for the selected channel doping level.

4. The device of claim 3, wherein said trenches have a width of about 0.3 to 0.5 microns.

5. The device of claim 3, wherein said pulse voltage has a peak of 4 to 10 volts.

6. The switching device of claim 1, wherein said polysilicon mass in said trenches is divided into first and second insulated masses.