Differential receiver

• US 20060017463A1
• Filed: 06/14/2005
• Published: 01/26/2006
• Est. Priority Date: 06/15/2004
• Status: Active Grant

• Current Assignee: Valera Pharmaceuticals, Inc. (Endo International PLC), STMicroelectronics Pvt Ltd. (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Pvt Ltd. (STMicroelectronics NV)
• Inventors: Chauhan, Rajat, Kasanyal, Sunil C.
• Granted Patent: US 7,348,802 B2
• Time in Patent Office: Days
• US Class Current: 326/82
• CPC Class Codes: H03K 19/00361 in field effect transistor circuits
• CPC Class Codes: H03K 19/018528 with at least one differential stage
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/0292 Arrangements specific to the receiver end

Abstract

A differential receiver includes a feedback circuit connected between an output node and one common node of the differential receiver to reduce the bandwidth and reject noise for a specific interval of time. In operation, a differential receiver bias current is controlled responsive to an output signal at the output node. Bias current is turned on during a steady-state mode with respect to the output signal, and is turned off, for a given delay period, in response to a transition mode with respect to the output signal.

Claims

1. A differential receiver, comprising:

a differential circuit having an output node and at least one common node; and

a feedback circuit connected between the output node and the at least one common node to reduce receiver bandwidth and reject noise for a specific interval of time.

2. The differential receiver in claim 1, wherein said feedback circuit comprises a pulse generator circuit, an output of said pulse generator circuit being connected to a control bias current circuit and a current mirror circuit coupled in series.

3. The differential receiver in claim 2, wherein said pulse generator circuit comprises a delay element and a logic gate, and an output of said delay element is connected to an input of said logic gate.

4. The differential receiver in claim 3, wherein said logic gate is an Ex-OR gate.

5. The differential receiver in claim 3, wherein said logic gate is an inverter.

6. The differential receiver in claim 3, wherein said delay element is one of a chain of inverters or a complex delay circuitry.

7. The differential receiver in claim 1, wherein said control bias current circuit comprises at least one transistor powered by a higher voltage supply.

8. The differential receiver in claim 1, wherein said current mirror circuit comprises at least two transistors connected to each other at their control nodes.

9. The differential receiver in claim 8, wherein said transistors are either P-MOS or N-MOS transistors.

10. A differential receiver, comprising:

a pair of differential input transistors coupled at a common node and whose gates receive a differential input signal;

a pair of load transistors coupled to the pair of differential input transistors to form at least one output node;

a current sink circuit coupled to the common node of the pair of differential input transistors; and

a feedback circuit coupled between the output node and the current sink circuit.

11. The differential receiver of claim 10 wherein the feedback circuit comprises a time delay circuit having an output and an input coupled to the output node and a logic circuit having an input coupled to the output of the time delay circuit and an output coupled to the current sink circuit.

12. The differential receiver of claim 11 wherein the logic circuit is a NOT gate.

13. The differential receiver of claim 11 wherein the logic circuit is an EX-OR gate having a first input coupled to the output of the time delay circuit and a second input coupled to the output node.

14. The differential receiver of claim 10 wherein the current sink circuit comprises a current mirror circuit having a mirror branch coupled to the common node and a reference branch whose current is controlled by the feedback circuit.

15. The differential receiver of claim 14 wherein the reference branch includes a transistor whose gate terminal is coupled to an output of the feedback circuit.

16. The differential receiver of claim 15 wherein the feedback circuit turns the reference branch on during a steady-state mode with respect to the output node and turns the reference branch off in response to a transition mode with respect to the output node.

17. The differential receiver of claim 16 wherein the feedback circuit includes a delay timing circuit for setting a certain amount of time that the reference branch is turned off in response to a transition mode with respect to the output node.

18. The differential receiver of claim 14 wherein the reference branch includes a first sub-branch and a second sub-branch whose operations are controlled by the feedback circuit.

19. The differential receiver of claim 18 wherein the feedback circuit turns one or the other of the first and second sub-branches on during a steady-state mode with respect to the output node and turns both of the first and second sub-branches off in response to a transition mode with respect to the output node.

20. The differential receiver of claim 19 wherein the feedback circuit includes a delay timing circuit for setting an certain amount of time that both of the first and second sub-branches are turned off in response to a transition mode with respect to the output node.

21. A method, comprising:

differentially receiving a signal to generate an output signal; and

controlling differential receiver bias current responsive to the output signal.

22. The method of claim 21 wherein controlling comprises:

turning bias current on during a steady-state mode with respect to the output signal; and

turning bias current off in response to a transition mode with respect to the output signal.

23. The method of claim 22 wherein turning bias current off comprises limiting an amount of time bias current is turned off to a certain delay period.

24. A method for rejecting noise signals by a differential receiver comprising:

detecting an input signal by the differential receiver; and

outputting a response from the differential receiver to a feedback circuit for reducing a current flowing through the differential receiver and thereby reducing a bandwith of the differential receiver in order to reject noise for a specific interval of time.