Pulse-based high-speed low-power gated flip-flop circuit

• US 20060017483A1
• Filed: 02/24/2005
• Published: 01/26/2006
• Est. Priority Date: 07/21/2004
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Min-Su
• Granted Patent: US 7,154,319 B2
• Time in Patent Office: Days
• US Class Current: 327/218
• CPC Class Codes: H03K 3/0372 of the master-slave type
• CPC Class Codes: H03K 3/356121 with synchronous operation H03K3/35613, H03K3/356147 take precedence

Abstract

A high-speed gated flip-flop includes a latch configured to generate a data output signal (Q) in response to a data input signal (D) and a pair of true and complementary clock pulses (GCP,GCPB). These clock pulses are provided by a clock generator responsive to a periodic clock signal (CK). A control circuit is also provided. The control circuit is coupled to a feedback node (ND2) in the pulse generator. The control circuit configured to selectively enable the pulse generator in response to an enable signal (/EN). The pulse generator is configured so that an active transition of the true clock pulse (GCP) is fed back to the feedback node (ND2) in a manner that resets the pulse generator and terminates the true and complementary clock pulses in-sync with the active (e.g., low-to-high) transition of the true clock pulse (GCP).

Claims

1. A gated flip-flop, comprising:

a latch configured to generate a data output signal in response to a data input signal and a pair of true and complementary clock pulses;

a pulse generator configured to generate the true and complementary clock pulses in response to a periodic clock signal; and

a control circuit coupled to a feedback node in said pulse generator, said control circuit configured to selectively enable said pulse generator in response to an enable signal.

2. The flip-flop of claim 1, wherein said control circuit is responsive to the periodic clock signal.

3. The flip-flop of claim 1, wherein said pulse generator is configured so that an active transition of the true clock pulse is fed back to the feedback node in a manner that resets said pulse generator and terminates the true and complementary clock pulses in-sync with the active transition of the true clock pulse.

4. The flip-flop of claim 1, wherein said latch and said control circuit are responsive to a set signal.

5. The flip-flop of claim 1, wherein said latch and said control circuit are responsive to a reset signal.

6. The flip-flop of claim 1, wherein said latch comprises a combinational input circuit responsive to the data input signal, a scan data input signal and true and complementary scan enable signals.

7. A gated flip-flop circuit comprising:

a pulse generator with a feedback node for generating gated clock pulse signals in synchronization with a clock signal, wherein any one of the gated clock pulse signals is fed back to the feedback node;

a latch for receiving and latching data in response to the gated clock pulse signals; and

a control circuit connected to the feedback node for controlling the feedback node in response to an enable signal such that the gated clock pulse signals are selectively generated in synchronization with the clock signal.

8. The gated flip-flop circuit according to claim 7, wherein the pulse generator comprises:

a NAND gate having one input terminal for receiving the clock signal, the other input terminal connected to the feedback node, and an output terminal for outputting a first gated clock pulse signal among the gated clock pulse signals;

an inverter for inverting an output of the NAND gate to output a second gated clock pulse signal; and

an NMOS transistor controlled by the second gated clock pulse signal and connected between the feedback node and ground.

9. The gated flip-flop circuit according to claim 7, wherein the control circuit prevents the feedback node from being floated during a high-level period or a low-level period of the clock signal.

10. The gated flip-flop circuit according to claim 7, wherein the control circuit comprises:

a first NMOS transistor connected between the feedback node and ground and controlled by the enable signal; and

first and second PMOS transistors connected in series between a power supply voltage and the feedback node,

wherein the first and second PMOS transistors are controlled by the enable signal and the clock signal, respectively.

11. The gated flip-flop circuit according to claim 9, wherein the control circuit further comprises:

an inverter having an input terminal connected to the feedback node; and

second and third NMOS transistors connected in series between the feedback node and ground,

wherein the second NMOS transistor is controlled by the clock signal and the third NMOS transistor is controlled by an output of the inverter.

12. The gated flip-flop circuit according to claim 11, wherein the second and third NMOS transistors and the inverter constitute a latch for storing a logic state of the feedback node.

13. A gated flip-flop circuit comprising:

a pulse generator with a feedback node for generating gated clock pulse signals in synchronization with a clock signal, wherein any one of the gated clock pulse signals is fed back to the feedback node;

a latch for receiving and latching data in response to the gated clock pulse signals; and

a control circuit connected to the feedback node for controlling the feedback node in response to an enable signal such that the gated clock pulse signals are selectively generated in synchronization with the clock signal,

wherein the control circuit comprises;

first and second PMOS transistors connected between a power supply voltage and the feedback node; and

a first NMOS transistor connected between the feedback node and ground,

wherein the first PMOS transistor and the first NMOS transistor are controlled by the enable signal and the second NMOS transistor is controlled by the clock signal.

14. The gated flip-flop circuit according to claim 13, wherein the control circuit prevents the feedback node from being floated during a high-level period or a low-level period of the clock signal.

15. The gated flip-flop circuit according to claim 14, wherein the control circuit further comprises:

a first inverter having an input terminal connected to the feedback node; and

second and third NMOS transistors connected in series between the feedback node and ground,

wherein the second NMOS transistor is controlled by the clock signal and the third NMOS transistor is controlled by an output of the first inverter.

16. The gated flip-flop circuit according to claim 15, wherein the second and third NMOS transistors and the first inverter constitute a latch for storing a logic state of the feedback node.

17. The gated flip-flop circuit according to claim 16, wherein the pulse generator comprises:

a NAND gate having one input terminal for receiving the clock signal, the other input terminal connected to the feedback node, and an output terminal for outputting a first gated clock pulse signal among the gated clock pulse signals;

a second inverter for inverting an output of the NAND gate to output a second gated clock pulse signal; and

an NMOS transistor controlled by the second gated clock pulse signal and connected between the feedback node and ground.

18. The gated flip-flop circuit according to claim 13, wherein an output of the latch is set to be a predetermined logic state by a preset signal.

19. The gated flip-flop circuit according to claim 18, wherein the control circuit controls the feedback node such that the logic states of the gated clock pulse signals remain constant during activation of the preset signal irrespective of the enable signal.

20. The gated flip-flop circuit according to claim 18, wherein the control circuit further comprises:

a third PMOS transistor connected between the power supply voltage and the first PMOS transistor and controlled by the preset signal; and

a second NMOS transistor connected between the feedback node and ground and controlled by the preset signal.

21. The gated flip-flop circuit according to claim 13, wherein an output of the latch is set to be a predetermined logic state by a reset signal.

22. The gated flip-flop circuit according to claim 21, wherein the control circuit controls the feedback node such that the logic states of the gated clock pulse signals remain constant during activation of the reset signal irrespective of the enable signal.

23. The gated flip-flop circuit according to claim 21, wherein the control circuit further comprises:

a third PMOS transistor connected between the power supply voltage and the first PMOS transistor and controlled by the reset signal; and

a second NMOS transistor connected between the feedback node and ground and controlled by the reset signal.

24. The gated flip-flop circuit according to claim 13, wherein the latch receives normal data or scan data depending on activation of a scan enable signal.

25. The gated flip-flop circuit according to claim 24, wherein the control circuit further comprises:

a third PMOS transistor connected between the power supply voltage and the second PMOS transistor and controlled by the scan enable signal; and

a second NMOS transistor connected between the first NMOS transistor and ground and controlled by the scan enable signal.

26. A gated flip-flop circuit comprising:

a pulse generator with a feedback node for generating gated clock pulse signals in synchronization with a clock signal;

a latch for receiving and latching data in response to the gated clock pulse signals; and

a control circuit connected to the feedback node for controlling the feedback node in response to an enable signal and the clock signal,

wherein the control circuit comprises;

first and second PMOS transistors connected in series between a power supply voltage and the feedback node, wherein the first and second PMOS transistors are controlled by the enable signal and the clock signal, respectively;

a first NMOS transistor connected between the feedback node and ground and controlled by the enable signal;

a first inverter having an input terminal connected to the feedback node; and

second and third NMOS transistors connected in series between the feedback node and ground, wherein the second NMOS transistor is controlled by the clock signal, and the third NMOS transistor is controlled by an output of the inverter.

27. A gated flip-flop circuit comprising:

a pulse generator with a feedback node for generating gated clock pulse signals in synchronization with a clock signal;

a latch for receiving and latching data in response to the gated clock pulse signals; and

a control circuit connected to the feedback node for controlling the feedback node in response to a preset signal, an enable signal, and the clock signal,

wherein the control circuit comprises;

first to third PMOS transistors connected in series between a power supply voltage and the feedback node, wherein the first to third PMOS transistors are controlled by the preset signal, the enable signal, and the clock signal, respectively;

a first NMOS transistor connected between the feedback node and ground and controlled by the preset signal;

a second NMOS transistor connected between the feedback node and ground and controlled by the enable signal;

an inverter having an input terminal connected to the feedback node; and

third and fourth NMOS transistors connected in series between the feedback node and ground, wherein the third NMOS transistor is controlled by the clock signal and the fourth NMOS transistor is controlled by an output of the inverter.

28. A gated flip-flop circuit comprising:

a pulse generator with a feedback node for generating gated clock pulse signals in synchronization with a clock signal;

a latch for receiving and latching data in response to the gated clock pulse signals; and

a control circuit connected to the feedback node for controlling the feedback node in response to a reset signal, an enable signal, and the clock signal,

wherein the control circuit comprises;

first to third PMOS transistors connected in series between a power supply voltage and the feedback node, wherein the first to third PMOS transistors are controlled by the reset signal, the enable signal, and the clock signal, respectively;

a first NMOS transistor connected between the feedback node and ground and controlled by the reset signal;

a second NMOS transistor connected between the feedback node and ground and controlled by the enable signal;

an inverter having an input terminal connected to the feedback node; and

third and fourth NMOS transistors connected in series between the feedback node and ground, wherein the third NMOS transistor is controlled by the clock signal and the fourth NMOS transistor is controlled by an output of the inverter.

29. A gated flip-flop circuit comprising:

a pulse generator with a feedback node for generating gated clock pulse signals in synchronization with a clock signal;

a latch for receiving and latching data in response to the gated clock pulse signals; and

a control circuit connected to the feedback node for controlling the feedback node in response to a scan enable signal, an enable signal, and the clock signal,

wherein the control circuit comprises;

first and second PMOS transistors connected in series between a power supply voltage and the feedback node, wherein the first and second PMOS transistors are controlled by the enable signal and the clock signal, respectively;

first and second NMOS transistors connected between the feedback node and ground, wherein the first and second NMOS transistors are controlled by the enable signal and the scan enable signal, respectively;

an inverter having an input terminal connected to the feedback node; and

third and fourth NMOS transistors connected in series between the feedback node and ground, wherein the third NMOS transistor is controlled by the clock signal and the fourth NMOS transistor is controlled by an output of the inverter.