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Pulse-based high-speed low-power gated flip-flop circuit

  • US 20060017483A1
  • Filed: 02/24/2005
  • Published: 01/26/2006
  • Est. Priority Date: 07/21/2004
  • Status: Active Grant
First Claim
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1. A gated flip-flop, comprising:

  • a latch configured to generate a data output signal in response to a data input signal and a pair of true and complementary clock pulses;

    a pulse generator configured to generate the true and complementary clock pulses in response to a periodic clock signal; and

    a control circuit coupled to a feedback node in said pulse generator, said control circuit configured to selectively enable said pulse generator in response to an enable signal.

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