Solid-state imaging apparatus and sampling circuit

• US 20060017714A1
• Filed: 04/07/2005
• Published: 01/26/2006
• Est. Priority Date: 07/20/2004
• Status: Active Grant

• Current Assignee: Collabo Innovations, Inc. (Wi-LAN Inc.)
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: Yonemoto, Kazuya
• Granted Patent: US 7,408,539 B2
• Time in Patent Office: Days
• US Class Current: 345/204
• CPC Class Codes: H04N 25/616 involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
• CPC Class Codes: H04N 25/677 for reducing the column or line fixed pattern noise
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array

Abstract

A solid-state imaging apparatus which prevents fixed pattern noise from occurring is provided, the fixed pattern noise having a correlation in a column direction (or a row direction) caused by non-uniformity of a sampling circuit itself. The solid state imaging apparatus comprises a sampling circuit in which a signal from a photodiode PD is sampled. And, the sampling circuit includes: a sampling capacitor C_SH for holding the signal from the photodiode PD; a sampling MOS switch M12 which (i) transmits the signal from the photodiode PD to the sampling capacitor C_SH, or (ii) blocks the transmission; and a damping capacitor C_DS connected to (i) one of a source electrode and a drain electrode of the sampling MOS switch M12 which is located closer to the sampling capacitor C_SH and (ii) a gate electrode of the sampling MOS switch M12.

Claims

1. A solid-state imaging apparatus comprising a sampling circuit in which a signal from a photodiode is sampled,

wherein said sampling circuit includes:

a sampling capacitor for holding the signal;

a sampling Metal Oxide Semiconductor (MOS) switch which is a MOS transistor that (i) transmits the signal to said sampling capacitor, or (ii) blocks the transmission; and

a first damping capacitor connected to (i) one of a source electrode and a drain electrode of said sampling MOS switch, the one electrode being located closer to said sampling capacitor and (ii) a gate electrode of said sampling MOS switch.

2. The solid-state imaging apparatus according to claim 1,

wherein a capacity of said first damping capacitor is expressed by (i) a capacity between the source electrode of said sampling MOS switch and a reference potential, (ii) a capacity between the drain electrode and the reference potential, and (iii) said sampling MOS switch specific capacity.

3. The solid-state imaging apparatus according to claim 1,

wherein said sampling circuit further includes:

a column-selecting MOS switch which turns on or off a connection between said sampling capacitor and an output line; and

a second damping capacitor which is a capacitor connected to (i) one of a source electrode and a drain electrode of said column-selecting MOS switch, the one electrode being located closer to said sampling capacitor and (ii) a gate electrode of said column-selecting MOS switch.

4. The solid-state imaging apparatus according to claim 3,

wherein a capacity of said second damping capacitor is expressed by (i) a capacity between the source electrode of said column-selecting MOS switch and a reference potential, (ii) a capacity between the drain electrode and the reference potential, (iii) said column-selecting MOS switch specific capacity, and (iv) said sampling MOS switch specific capacity.

5. The solid-state imaging apparatus according to claim 3,

wherein said sampling circuit further includes a bias voltage application circuit in which a bias voltage is applied to the output line, and

in said bias voltage application circuit, the bias voltage to be applied to the output line is changed in synchronization with a control signal that turns off said column-selecting MOS switch.

6. The solid-state imaging apparatus according to claim 1,

wherein said sampling circuit further includes:

a clamp capacitor which is a capacitor connected between (i) a column signal line that transmits the signal from the photodiode and (ii) said sampling MOS switch; and

a clamp voltage application circuit in which a clamp voltage is applied to said clamp capacitor, and

the signal transmitted from the photodiode is correlated double sampled.

7. The solid-state imaging apparatus according to claim 1,

wherein said sampling circuit further includes:

a clamp capacitor which is a capacitor connected between said sampling MOS switch and said sampling capacitor; and

a clamp voltage application circuit in which a clamp voltage is applied to said clamp capacitor, and

the signal transmitted from said photodiode is correlated double sampled.

8. The solid-state imaging apparatus according to claim 1, comprising two of said sampling circuits per one column of photodiodes, and

the two sampling circuits are connected to each other in parallel so that one column signal line can be used for a common input, said column signal line transmitting a signal from the one column of photodiodes.

9. The solid-state imaging apparatus according to claim 8,

wherein said sampling circuit further includes a column-selecting MOS switch which is a MOS switch that turns on or off the connection between said sampling capacitor and the output line, and

when the signal held in said sampling capacitor is outputted to the output line, said column-selecting MOS switch is brought into a conduction state from a non-conduction state, then brought into the non-conduction state again.

10. The solid-state imaging apparatus according to claim 1,

wherein said first damping capacitor is made up of (i) one of a source electrode and a drain electrode of said sampling MOS switch, the one electrode being located closer to said sampling capacitor, (ii) a gate electrode of said sampling MOS switch and (iii) a gate oxide film of the sampling MOS switch sandwiched between said two electrodes.

11. A sampling circuit in which a signal from a solid-state imaging device is sampled, the circuit including:

a sampling capacitor which is a capacitor for holding the signal;

a sampling MOS switch which is a MOS transistor that (i) transmits the signal to said sampling capacitor, or (ii) blocks the transmission; and

a first damping capacitor which is a capacitor connected to (i) one of a source electrode and a drain electrode of said sampling MOS switch, the one electrode being located closer to said sampling capacitor and (ii) a gate electrode of said sampling MOS switch.

12. The sampling circuit according to claim 11, further including:

a column-selecting MOS switch which is a MOS switch that turns on or off a connection between said sampling capacitor and an output line; and

a second damping capacitor which is a capacitor connected to (i) one of a source electrode and a drain electrode of said column-selecting MOS switch, the one electrode being located closer to said sampling capacitor and (ii) a gate electrode of said column-selecting MOS switch.