Apparatus and method of driving memory for display device

• US 20060017719A1
• Filed: 10/07/2004
• Published: 01/26/2006
• Est. Priority Date: 07/22/2004
• Status: Active Grant

• Current Assignee: Msyslab Company Limited
• Original Assignee: Msyslab Company Limited
• Inventors: Park, Jong Hoon
• Granted Patent: US 7,505,301 B2
• Time in Patent Office: Days
• US Class Current: 345/213
• CPC Class Codes: G09G 2310/0275 Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
• CPC Class Codes: G09G 2360/18 Use of a frame buffer in a display terminal, inclusive of the display panel
• CPC Class Codes: G09G 3/2092 Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165

Abstract

A display driver having Dynamic Random Access Memory (DRAM) cells and a method of controlling the timing of the display driver are disclosed. The display driver includes memory cells each of which is implemented using a DRAM cell having a single transistor and a single capacitor. The display driver includes a drive control unit generating a scan signal, a refresh signal and a write/read signal, a word line drive unit driving word lines of the memory cells, and a data input/output unit for controlling input/output of data to/from the memory cells. The display driver gives priority to a write/read operation over a refresh operation and a scan operation.

Claims

1. A display driver, comprising:

a memory array having memory cells arranged in a matrix form defined by rows and columns, each of the memory cells being a Dynamic Random Access Memory (DRAM) cell in which a refresh operation is performed at a regular refresh period to maintain stored data;

a drive control unit for generating a scan signal, a refresh signal and a write/read signal to control a scan operation in which data of the memory array is scanned and transmitted to a display panel in response to the scan signal, a refresh operation in which the memory array is refreshed in response to the refresh signal, and a write/read operation in which data of an external system is written/read into/from the memory cells in response to the write/read signal, respectively;

a word line drive unit for providing a word line drive signal to the memory array, the word line drive signal activating a word line of corresponding one of the memory cells; and

a data input/output unit for controlling input/output of data to/from the memory cells of the memory array, amplifying data of bit lines of the memory cells, forming a transmission path toward the external system during the write/read operation, and forming a transmission path toward the display panel during the scan operation.

2. The display driver as set forth in claim 1, wherein the drive control unit gives priority to the write/read operation so that the scan and refresh operations are stopped when the write/read operation is performed.

3. The display driver as set forth in claim 1, wherein the word line is activated in response to activation of one of the scan signal, the refresh signal and the write/read signal.

4. The display driver as set forth in claim 1, wherein the scan signal is activated in response to a first direction transition edge of a clock signal, and the refresh signal is activated in response to a second direction transition edge of the clock signal.

5. The display driver as set forth in claim 4, wherein the first direction transition edge of the clock signal is a rising edge of the clock signal, and the second direction transition edge of the clock signal is a falling edge of the clock signal.

6. The display driver as set forth in claim 1, further including a latch unit connected between the data input/output unit and the display panel, the latch unit latching data transmitted from the data input/output unit.

7. The display driver as set forth in claim 1, wherein the transmission path from the data input/output unit to the display panel is formed in response to the scan signal.

8. The display driver as set forth in claim 1, wherein the data of bit lines is amplified in response to the refresh signal.

9. A method of controlling timing of a display driver having memory cells each of which is a DRAM cell, comprising:

performing a scan operation of scanning data in the memory cells and transmitting the scanned data to a display panel; and

performing a refresh operation of refreshing the memory cells;

wherein the scan operation is performed in response to a first direction transition edge of a clock signal, and the refresh operation is performed in response to a second direction transition edge of the clock signal.

10. The method as set forth in claim 9, further comprising:

applying a write/read command to write/read input data into/from the memory cells and providing addresses of the memory cells, while the scan operation is performed;

stopping the scan operation in response to the write/read command;

latching data, which is scanned during the scan operation, in response to the write/read command; and

writing the input data into the memory cells specified by the addresses in response to the write/read command.

11. The method as set forth in claim 9, further comprising:

applying a write command signal to write data into the memory cells and providing addresses of the memory cells, while the refresh operation is performed;

stopping the refresh operation in response to the write command; and

writing the input data into the memory cells specified by the addresses in response to the write command.

12. The method as set forth in any of claim 9, wherein the first direction transition edge of the clock signal is a rising edge of the clock signal, and the second direction transition edge of the clock signal is a falling edge of the clock signal.

13. A method of controlling timing of a display driver including a memory array having memory cells arranged in a matrix form defined by rows and columns, each of the memory cells being a DRAM cell in which a refresh operation is performed at a regular refresh period to maintain stored data, the method comprising:

granting priority to a write/read operation when a scan operation of scanning data from the memory array and transmitting the scanned data to a display panel, a refresh operation of refreshing the memory array, and a write/read operation of writing/reading data into/from the memory cells are simultaneously requested to be performed; and

stopping the scan and refresh operations while the write/read operation is performed.

14. The method as set forth in claim 13, wherein the scan operation is performed in response to a first direction transition edge of a clock signal and the refresh operation is performed in response to a second direction transition edge of the clock signal, so that the scan and refresh operations are prevented from being simultaneously performed.

15. The method as set forth in claim 14, wherein the first direction transition edge of the clock signal is a rising edge of the clock signal, and the second direction transition edge of the clock signal is a falling edge of the clock signal.