Laser diode arrays with reduced heat induced strain and stress

• US 20060018355A1
• Filed: 07/23/2004
• Published: 01/26/2006
• Est. Priority Date: 07/23/2004
• Status: Abandoned Application

• Current Assignee: Comlasc Nt-AB
• Original Assignee: Comlasc Nt-AB
• Inventors: Feitisch, Alfred, Blixt, Peter, Lindstroem, Carsten
• Application Number:
  US10/897,560
• Publication Number:
  US 20060018355A1
• Time in Patent Office: Days
• US Class Current: 372/50.120
• CPC Class Codes: H01S 5/02345 Wire-bonding
• CPC Class Codes: H01S 5/0237 by soldering
• CPC Class Codes: H01S 5/02423 Liquid cooling, e.g. a liquid cools a mount of the laser
• CPC Class Codes: H01S 5/02476 Heat spreaders, i.e. improving heat flow between laser chip and heat dissipating elements
• CPC Class Codes: H01S 5/028 Coatings ; Treatment of the laser facets, e.g. etching, passivation layers or reflecting layers
• CPC Class Codes: H01S 5/0281 Coatings made of semiconductor materials
• CPC Class Codes: H01S 5/4025 Array arrangements, e.g. constituted by discrete laser diodes or laser bar H01S5/42 takes precedence

Abstract

A laser diode array has a semiconductor layered structure that includes at least one active layer. A heat sink is coupled to semiconductor layered structure. A plurality of laser emitters are formed in the active layer. A majority of the plurality of laser emitters have a spacing between adjacent laser emitters that provides for a more uniform heat distribution.

Claims

1. A laser diode array, comprising:

a semiconductor layered structure including at least one active layer;

a heat sink coupled to semiconductor layered structure; and

a plurality of laser emitters formed in the active layer, a majority of the plurality of laser emitters having a spacing between adjacent laser emitters that provides for a more uniform heat distribution.

2. The of claim 1, wherein the spacing is the distance between adjacent laser emitters.

3. The array of claim 1, wherein the laser emitters are arranged as a linear array.

4. The array of claim 1, wherein at least a portion of the plurality of laser emitters include a crystal mirror facet.

5. The array of claim 4, wherein the at least a portion of the plurality of laser emitters that include a crystal mirror facet that includes at least one group III element.

6. The array of claim 4, wherein at least a portion of the crystal mirror facets is covered with at least one layer of dielectric material to form a laser mirror.

7. The array of claim 6, wherein the dielectric material is selected from the group Al₂O₃, SiO₂, Silicon, Germanium, Ta₂O₅, HfO₂, Ti₂O₅, Sc₂O₃, Nb₂O₅, AlN, Si₃N₄, InN, GaN and oxi-nitrides of Aluminum, Indium, Gallium, Silicon, Tantalum, Hafnium, Scandium and Titanium and Niobium

8. The array of claim 4, wherein at least a portion of crystal mirror facets is covered with at least two layers of a dielectric material.

9. The array of claim 8, wherein the at least two layers of dielectric material are selected from one or more of Al₂O₃, SiO₂, Silicon, Germanium, Ta₂O₅, HfO₂, Ti₂O₅, Sc₂O₃, Nb₂O₅, AlN, Si₃N₄, InN, GaN and oxi-nitrides of Aluminum, Indium, Gallium, Silicon, Tantalum, Hafnium, Scandium, Titanium and Niobium

10. The array of claim 1, wherein the more uniform heat distribution provides for reduced heat induced strain and stress between the semiconductor and the heat sink.

11. The array of claim 1, wherein the more uniform heat distribution provides for reduced heat induced strain in the at least one active layer.

12. The array of claim 1, wherein the spacing between at least two adjacent laser emitters is no greater than 100 microns.

13. The array of claim 1, wherein the spacing between at least two adjacent laser emitters is no greater than 90 microns.

14. The array of claim 1, wherein the spacing between at least two adjacent laser emitters is no greater than 80 microns.

15. The array of claim 1, wherein the spacing between at least two adjacent laser emitters is no greater than 70 microns.

16. The array of claim 1, wherein the spacing between at least two adjacent laser emitters is no greater than 60 microns.

17. The array of claim 1, wherein the spacing between at least two adjacent laser emitters is no greater than 50 microns.

18. The array of claim 1, wherein the array has a metallized n doped surface and a metallized p doped surface that is metallized at least at the location of the pluralty of laser emitters that is formed in the active layer.

19. The array of claim 1, wherein a majority of the plurality of laser emitters have a laser emitter width of 1 micron to 250 microns.

20. The array of claim 19, wherein a plane of the width is parallel, to within 20%, relative to a direction of the spacing between adjacent laser emitters

21. The array of claim 1, wherein a majority of the plurality of laser emitters are transverse single mode and longitudinally multi-mode.

22. The array of claim 1, wherein a majority of the plurality of laser emitters are transverse single mode and longitudinally single mode.

23. The array of claim 1, wherein a majority of the plurality of laser emitters are transverse multi mode, and longitudinal multi mode.

24. The array of claim 1, wherein the array produces an output with a wavelength of at least 200 nm.

25. The array of claim 1, wherein the thin layer semiconductor material includes a III-V semiconductor material.

26. The array of claim 1, wherein the semiconductor material is selected from AlGaN, AlInGaP, AlGaAs, InGaAsP, InGaN, InGaP, AlInGaAs, InP, GaN, GaP, InGaAs, and GaAs.

27. The array of claim 18, wherein the n doped metallized surface is mounted to the heat sink that provides heat removal.

28. The array of claim 18, wherein the n doped metallized surface is mounted to the heat sink and coupled to an electrical connection.

29. The array of claim 18, wherein the p doped metallized surface is coupled to an electrical connection.

30. The array of claim 18, wherein the p doped metallized surface is mounted to the heat sink that provides heat removal.

31. The array of claim 18, wherein the p doped metallized surface is mounted to the heat sink and coupled to an electrical connection.

32. The array of claim 18, wherein the n doped metallized surface is coupled to an electrical connection.

33. The array of claim 18, further comprising:

a sub-mount positioned between the heat sink and the layered semiconductor structure.

34. The array of claim 33, wherein the sub-mount has a face with dimensions that are substantially the same as the metallized n doped surface.

35. The array of claim 33, wherein the sub-mount has a face with dimensions that are substantially the same as the metallized p doped surface.

36. The array of claim 33, wherein the submount has a face with dimensions larger than the metallized n-doped surface.

37. The array of claim 33, wherein the submount has a face with dimensions larger than the metallized p-doped surface.

38. The array of claim 33, wherein the submount has a thermal expansion coefficient that is at least 20% of a thermal expansion coefficient of the layered semiconductor structure.

39. The array of claim 33, wherein the submount is made of a material that provides heat conductivity.

40. The array of claim 33, wherein the submount is made of material that provides electrical conductivity.

41. The array of claim 33, where the submount is made of material that does not provide electrical conductivity.

42. The array of claim 33, wherein a first bonding agent is positioned between the submount and the layered semiconductor structure.

43. The array of claim 33, wherein a second bonding agent is positioned between submount and the heat sink.

44. The array of claim 42, wherein the first bonding agent is a metal or a solder.

45. The array of claim 42, wherein the first bonding agent is made of a material that has a melting point less than a melting point of the layered semiconductor structure.

46. The array of claim 42, wherein the first bonding agent is made of a material that provides heat conductivity.

47. The array of claim 42, wherein the first bonding agent is made of material that provides electrical conductivity.

48. The array of claim 43, where the second bonding agent is made of material that does not provide electrical conductivity.

49. The array of claim 43, wherein the second bonding agent is a metal or a solder.

50. The array of claim 43, wherein the second bonding agent is made of a material that provides heat conductivity.

51. The array of claim 43, wherein the second bonding agent is made of material that provides electrical conductivity.

52. The array of claim 1, further comprising:

a first bonding agent positioned between the heat sink and the layered semiconductor structure.

53. The array of claim 52, wherein the first bonding agent is a metal or a solder.

54. The array of claim 52, wherein the first bonding agent is made of a material that has a melting point less than a melting point of the layered semiconductor structure.

55. The array of claim 52, wherein the first bonding agent is made of a material that provides heat conductivity.

56. The array of claim 52, wherein the first bonding agent is made of material that provides electrical conductivity.

57. The array of claim 1, wherein the plurality of laser emitters are made from the at least one active layer of the semiconductor.

58. The array of claim 57, wherein the at least one active layer is positioned between waveguide layers of the semiconductor.

59. The array of claim 1, wherein the heat sink is a material selected from, metal, metal containing composition, ceramic, carbide, glass, crystalline material and a semiconductor material.

60. The array of claim 33, wherein the heat sink is a material selected from, metal, metal containing composition, ceramic, carbide, glass, crystalline material and a semiconductor material.

61. The array of claim 48, wherein the heat sink is a material selected from, metal, metal containing composition, ceramic, carbide, glass, crystalline material and a semiconductor material.

62. The array of claim 1, wherein the heat sink includes channels configured to receive a cooling medium.

63. The array of claim 33, wherein the heat sink includes channels configured to receive a cooling medium.

64. The array of claim 48, wherein the heat sink includes channels configured to receive a cooling medium.

65. The array of claim 1, wherein the heat sink is optically contacted to the layered semiconductor structure.

66. The array of claim 1, wherein the heat sink is diffusion bonded to the layered semiconductor structure.

67. The array of claim 1, wherein the array is operated continuous wave (cw).

68. The array of claim 1, wherein the array is operated pulsed.

69. The array of claim 1, wherein the array produces a pulsed output with pulse widths of at least 100 micro seconds and duty cycles of less than 100%.

70. The array of claim 1, wherein the array is operated quasi-cw.

71. The array of claim 1, wherein the array produces a quasi cw output with pulse widths of less than 100 micro seconds and duty cycles of less than 100%.

113. The method of claim 112, wherein the spacing between at least two adjacent laser emitters is no greater than 100 microns.

72. A laser diode array, comprising:

a layered semiconductor structure with at least one active layer;

a heat sink coupled to the layered semiconductor structure; and

a plurality of laser emitters formed in the at least one active layer, at least a portion of the plurality of laser emitters having a spacing between adjacent laser emitters that is no greater than 50 microns.

73. The array of claim 72, wherein the plurality of laser emitters are arranged as a linear array.

74. The array of claim 72, wherein at least a portion of the plurality of laser emitters include a crystal mirror facet.

75. The array of claim 72, wherein the at least a portion of the plurality of laser emitters that includes a crystal mirror facet that includes at least one group III element.

76. The array of claim 74, wherein at least a portion of the crystal mirror facets is covered with at least one layer of dielectric material to form a laser mirror.

77. The array of claim 74, wherein at least a portion of crystal mirror facets is covered with at least two layers of a dielectric material.

78. The array of claim 72, wherein the array has a metallized n doped surface and a metallized p doped surface that is metallized at least at the location of the emitter that is formed in the active layer.

79. The array of claim 72, wherein a majority of the plurality of laser emitters have a laser emitter width of 1 micron to 250 microns.

80. The array of claim 79, wherein a plane of the width is parallel, to within 20%, relative to a direction of the spacing between adjacent emitters

81. The array of claim 72, wherein a majority of the plurality of laser emitters are transverse single mode and longitudinally multi-mode.

82. The array of claim 72, wherein a majority of the plurality of laser emitters are transverse single mode and longitudinally single mode.

83. The array of claim 72, wherein a majority of the plurality of laser emitters are transverse multi mode, and longitudinal multi mode.

84. The array of claim 72, wherein the array produces an output with a wavelength of at least 200 nm.

85. The array of claim 72, wherein the semiconductor material includes a III-V semiconductor material.

86. The array of claim 72, wherein the semiconductor material is selected from AlGaN, AlInGaP, AlGaAs, InGaAsP, InGaN, InGaP, AlInGaAs, InP, GaN, GaP, InGaAs, and GaAs.

87. The array of claim 78, wherein the n doped metallized surface is mounted to the heat sink that provides heat removal.

88. The array of claim 78, wherein the n doped metallized surface is mounted to the heat sink and coupled to an electrical connection.

89. The array of claim 78, wherein the p doped metallized surface is coupled to an electrical connection.

90. The array of claim 78, wherein the p doped metallized surface is mounted to the heat sink that provides heat removal.

91. The array of claim 78, wherein the p doped metallized surface is mounted to the heat sink and coupled to an electrical connection.

92. The array of claim 78, wherein the n doped metallized surface is coupled to an electrical connection.

93. The array of claim 78, further comprising:

a sub-mount positioned between the heat sink and the layered semiconductor structure.

94. The array of claim 93, wherein the sub-mount has a face with dimensions that are substantially the same as the metallized n doped surface.

95. The array of claim 93, wherein the submount has a face with dimensions larger than the metallized n-doped surface.

96. The array of claim 93, wherein the sub-mount has a face with dimensions that are substantially the same as the metallized p doped surface.

97. The array of claim 93, wherein the submount has a face with dimensions larger than the metallized p-doped surface.

98. The array of claim 93, wherein the submount has a thermal expansion coefficient that is at least 20% of a thermal expansion coefficient of the layered semiconductor structure.

99. The array of claim 93, wherein the submount is made of a material that provides heat conductivity.

100. The array of claim 93, wherein the submount is made of material that provides electrical conductivity.

101. The array of claim 93, where the submount is made of material that does not provide electrical conductivity.

102. The array of claim 93, wherein a first bonding agent is positioned between the submount and the layered semiconductor structure.

103. The array of claim 93, wherein a second bonding agent is positioned between submount and the heat sink.

104. The array of claim 72, further comprising:

a first bonding agent positioned between the heat sink and the layered semiconductor structure.

105. The array of claim 72, wherein the plurality of laser emitters are made from at least one active layer of the semiconductor.

106. The array of claim 105, wherein the active layers are positioned between waveguide layers of the semiconductor.

107. The array of claim 72, wherein the array is operated continuous wave (cw).

108. The array of claim 72, wherein the array is operated pulsed.

109. The array of claim 72, wherein the array produces a pulsed output with pulse widths of at least 100 micro seconds and duty cycles of less than 100%.

110. The array of claim 72, wherein the array is operated quasi-cw.

111. The array of claim 72, wherein the array produces a quasi cw output with pulse widths of less than 100 micro seconds and duty cycles of less than 100%.%

112. A method of producing a output from a laser diode array, comprising:

providing a laser diode array that has a layered semiconductor structure with at least one active layer and a plurality of laser emitters formed in the at least one active layer;

providing a spacing for at least a portion of the adjacent laser emitters to create a more uniform heat distribution.

removing heat from the semiconductor with a heatsink; and

producing an output beam

114. The method of claim 112, wherein the spacing between at least two adjacent laser emitters is no greater than 90 microns.

115. The method of claim 112, wherein the spacing between at least two adjacent laser emitters is no greater than 80 microns.

116. The method of claim 112, wherein the spacing between at least two adjacent laser emitters is no greater than 70 microns.

117. The method of claim 112, wherein the spacing between at least two adjacent laser emitters is no greater than 60 microns.

118. The method of claim 112, wherein the spacing between at least two adjacent laser emitters is no greater than 50 microns.

119. The method of claim 112, wherein the more uniform heat distribution provides for reduced heat induced strain and stress between the semiconductor and the heat sink.

120. The method of claim 112, wherein the more uniform heat distribution provides for reduced heat induced strain in the at least one active layer.

121. The method of claim 112, wherein the output has a wavelength of at least 200 nm.

122. The method of claim 112, wherein the output is a pulsed output.

123. The method of claim 112, wherein the output is pulsed with pulse widths of at least 100 micro seconds and duty cycles of less than 100%.

124. The method of claim 112, wherein the output as a quasi-cw output.

125. The method of claim 112, wherein the output is a quasi cw output with pulse widths of less than 100 micro seconds and duty cycles of less than 100%.