Termination for trench MIS device having implanted drain-drift region

• US 20060019448A1
• Filed: 09/21/2005
• Published: 01/26/2006
• Est. Priority Date: 03/26/2004
• Status: Active Grant

• Current Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Inventors: Chen, Qufei, Darwish, Mohamed N., Qi, Jainhai, Terrill, Kyle W.
• Granted Patent: US 7,268,032 B2
• Time in Patent Office: Days
• US Class Current: 438/270
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench MIS device is formed in a P-epitaxial layer that overlies an N-epitaxial layer and an N+ substrate. In one embodiment, the device includes an N-type drain-drift region that extends from the bottom of the trench to the N-epitaxial layer. Preferably, the drain-drift region is formed at least in part by fabricating spacers on the sidewalls of the trench and implanting an N-type dopant between the sidewall spacers and through the bottom of the trench. The drain-drift region can be doped more heavily than the conventional “drift region” that is formed in an N-epitaxial layer. Thus, the device has a low on-resistance. The device can be terminated by a plurality of polysilicon-filled termination trenches located near the edge of the die, with the polysilicon in each termination trench being connected to the mesa adjacent the termination trench. The polysilicon material in each termination trenches.

Claims

1. A method of forming a semiconductor die containing an MIS device comprising:

providing a semiconductor substrate;

forming an epitaxial layer of a first conductivity type on said substrate, said substrate having a net doping concentration of a second conductivity type opposite to said first conductivity type;

etching a plurality of trenches in said epitaxial layer thereby forming a plurality of mesas between said trenches and between one of said trenches and an edge of said die, said trenches extending from a surface of said epitaxial layer and having bottoms in said epitaxial layer, said trenches comprising active trenches and termination trenches, said mesas comprising active mesas between said active trenches and termination mesas between said termination mesas between said one of said trenches and said edge of said die;

introducing a dopant of said second conductivity type through the bottoms of said active trenches and said termination trenches to form a region of said second conductivity type extending between each of said trenches and said substrate;

forming an oxide layer on the walls of said trenches;

filling said trenches with a conductive material;

implanting a dopant of said second conductivity type into said layer so as to form source regions adjacent said active trenches while preventing said dopant from entering said layer in locations adjacent said termination trenches;

forming a dielectric layer over the surface of said first layer;

masking and etching said dielectric layer so as to form openings over said source regions, said termination trenches and said termination mesas;

depositing metal over said dielectric layer and said openings;

masking and etching said metal so as to form a source metal layer extending into said openings over said source regions and a plurality of termination metal layers, said termination metal layers being electrically isolated from each other, each of said termination metal layers extending into one of said openings over said termination trenches and one of said openings over said termination mesas and electrically connecting the conductive material in one of said termination trenches and a termination mesa.

2. The method of claim 1 comprising implanting a dopant of said first conductivity type through said openings in said dielectric layer over said termination mesas to form contact regions.

3. The method of claim 1 wherein providing a semiconductor substrate comprises forming a second epitaxial layer of said second conductivity type on a semiconductor member of said second conductivity type.