Transistor fabrication methods using dual sidewall spacers

• US 20060019456A1
• Filed: 07/26/2004
• Published: 01/26/2006
• Est. Priority Date: 07/26/2004
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Bu, Haowen, Khamankar, Rajesh, Hall, Lindsey, Chidambaram, PR
• Granted Patent: US 7,217,626 B2
• Time in Patent Office: Days
• US Class Current: 438/303
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

Methods (50) are presented for transistor fabrication, in which first and second sidewall spacers (120a, 120b) are formed laterally outward from a gate structure (114), after which a source/drain region (116) is implanted. The method (50) further comprises removing all or a portion of the second sidewall spacer (120b) after implanting the source/drain region (116), where the remaining sidewall spacer (120a) is narrower following the source/drain implant to improve source/drain contact resistance and PMD gap fill, and to facilitate inducing stress in the transistor channel.

Claims

1. A method of fabricating a transistor, the method comprising:

forming a gate structure over a channel region of a semiconductor body;

forming a first sidewall spacer along a lateral side of the gate structure;

forming a second sidewall spacer along a lateral side of the first sidewall spacer;

performing a deep source/drain implant to implant dopants into a source/drain region of the semiconductor body after forming the second sidewall spacer; and

removing at least a portion of the second sidewall spacer after the deep source/drain implant.

2. The method of claim 1:

wherein forming the first sidewall spacer comprises;

forming a first sidewall spacer material over the gate structure and over the source/drain region of the semiconductor body, and

performing a first anisotropic etch process to selectively remove the first sidewall spacer material from over the gate structure and from an outer portion of the source/drain region, leaving the first sidewall spacer along the lateral side of the gate structure over a portion of the source/drain region; and

wherein forming the second sidewall spacer comprises;

forming a second sidewall spacer material over the gate structure, over the first sidewall spacer, and over the outer portion of the source/drain region, and

performing a second anisotropic etch process to selectively remove the second sidewall spacer material from over the gate structure and from part of the outer portion of the source/drain region, leaving the second sidewall spacer along the lateral side of the first sidewall spacer.

3. The method of claim 2, wherein the first and second sidewall spacer materials are different.

4. The method of claim 3, wherein removing at least a portion of the second sidewall spacer comprises performing a third etch process to remove at least a portion of the second sidewall spacer material after the deep source/drain implant, the third etch process being selective to the first sidewall spacer material.

5. The method of claim 2, wherein forming the first sidewall spacer comprises depositing Si_WC_XN_Y or Si_WC_XN_YO_Z using a BTBAS precursor, and wherein forming the second sidewall spacer material comprises depositing silicon nitride with substantially no carbon.

6. The method of claim 5, wherein removing at least a portion of the second sidewall spacer comprises performing a third etch process to remove at least a portion of the second sidewall spacer material after the deep source/drain implant, the third etch process being selective to the first sidewall spacer material.

7. The method of claim 5, wherein removing at least a portion of the second sidewall spacer comprises wet etching the second sidewall spacer material using phosphoric acid at a temperature of about 160 degrees C. after the deep source/drain implant.

8. The method of claim 5, wherein removing at least a portion of the second sidewall spacer comprises reducing a lateral width of the second sidewall spacer by about 100 Å

or more after the deep source/drain implant.

9. The method of claim 5, further comprising forming a stress inducing material over the gate and the first sidewall spacer after removing at least a portion of the second sidewall spacer.

10. The method of claim 1, wherein the first and second sidewall spacers are of different materials.

11. The method of claim 1, wherein removing at least a portion of the second sidewall spacer comprises performing an etch process to remove at least a portion of the second sidewall spacer material after the deep source/drain implant, the etch process being selective to the first sidewall spacer.

12. The method of claim 1, wherein the first sidewall spacer comprises Si_WC_XN_Y or Si_WC_XN_YO_Z, and wherein the second sidewall spacer comprises silicon nitride with substantially no carbon.

13. The method of claim 12, wherein removing at least a portion of the second sidewall spacer comprises wet etching the second sidewall spacer material using phosphoric acid at a temperature of about 160 degrees C. after the deep source/drain implant.

14. The method of claim 12, wherein removing at least a portion of the second sidewall spacer comprises reducing a lateral width of the second sidewall spacer by about 100 Å

or more after the deep source/drain implant.

15. The method of claim 1, further comprising forming a stress inducing material over the gate and the first sidewall spacer after removing at least a portion of the second sidewall spacer.

16. A method of fabricating a transistor, the method comprising:

forming first and second sidewall spacers laterally outward from a gate structure, the first sidewall spacer extending between a lateral side of the gate structure and the second sidewall spacer;

implanting a source/drain region of a semiconductor body after forming the first and second sidewall spacers; and

removing substantially all of the second sidewall spacer after implanting the source/drain region.

17. The method of claim 16, wherein the first and second sidewall spacers are of different materials.

18. The method of claim 17, wherein removing substantially all of the second sidewall spacer comprises performing an etch process to remove substantially all of the second sidewall spacer material after the deep source/drain implant, the etch process being selective to the first sidewall spacer.

19. The method of claim 16, further comprising forming a stress inducing material over the gate and the first sidewall spacer after removing at least a portion of the second sidewall spacer.

20. The method of claim 16, wherein removing substantially all of the second sidewall spacer comprises reducing a lateral width of the second sidewall spacer by about 100 Å

or more after the deep source/drain implant.