Allocating resources to partitions in a partitionable computer

• US 20060020769A1
• Filed: 07/23/2004
• Published: 01/26/2006
• Est. Priority Date: 07/23/2004
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Morrison, John A., Kaufman, Gerald J. Jr., Herrell, Russ
• Granted Patent: US 7,606,995 B2
• Time in Patent Office: Days
• US Class Current: 712/13
• CPC Class Codes: G06F 9/5077 Logical partitioning of resources; Management or configuration of virtualized resources specific details on emulation or internal functioning of virtual machines G06F9/455

Abstract

Techniques are provided for allocating a plurality of resources on a chip to a plurality of partitions in a partitionable computer system. In one embodiment, a resource allocated to a first partition generates a physical address in an address space allocated to the first partition. A partition identification value identifies the first partition. The first partition identification value is stored in the first physical address to produce a partition-identifying address, which may be transmitted to a system fabric. In another embodiment, a transaction is received which includes a source terminus identifier identifying a source device which transmitted the transaction. It is determined, based on the source terminus identifier, whether the source device is allocated to the same partition as any of the plurality of resources. If the source device is so allocated, the transaction is transmitted to a resource that is allocated to the same partition as the source device.

Claims

1. A partitionable computer system partitioned into a plurality of partitions, the computer system comprising an integrated circuit, the integrated circuit comprising a first hardware resource allocated to a first one of the plurality of partitions and a second hardware resource allocated to a second one of the plurality of partitions that differs from the first one of the plurality of partitions.

2. The computer system of claim 1, wherein the integrated circuit comprises a processor and wherein the first and second hardware resources respectively comprise a first and second processor core.

3. The computer system of claim 1, wherein the integrated circuit comprises an input/output controller and wherein the first and second hardware resources respectively comprise a first and second input/output port.

4. The computer system of claim 1, wherein the first hardware resource comprises means for outputting a first physical address in a first address space allocated to the first one of the plurality of partitions, and wherein the computer system further comprises:

first partition identification means for storing a first partition identification value identifying the first one of the plurality of partitions; and

first bit substitution means, coupled to the first hardware resource and the first partition identification means, for producing a first partition-identifying address by storing the first partition identification value in at least part of the first physical address.

5. The computer system of claim 4, further comprising:

a system fabric; and

means for transmitting the first partition-identifying address over the system fabric.

6. The computer system of claim 4, wherein the second hardware resource comprises means for outputting a second physical address in a second address space allocated to the second one of the plurality of partitions, and wherein the computer system further comprises:

second partition identification means for storing a second partition identification value identifying the second one of the plurality of partitions; and

second bit substitution means, coupled to the second hardware resource and the second partition identification means, for producing a second partition-identifying address by storing the second partition identification value in at least part of the second physical address.

7. The computer system of claim 6, further comprising:

a system fabric; and

means for transmitting the second partition-identifying address over the system fabric.

8. The computer system of claim 6, wherein the first partition identification value has a first size and wherein the second partition identification value has a second size which differs from the first size.

9. The computer system of claim 4, further comprising:

a cache; and

means for transmitting the first partition-identifying address to the cache.

10. The computer system of claim 6, further comprising:

an address mapper coupled to the cache to map the first physical address into a first system address, the first system address including the first partition identification value.

11. The computer system of claim 4, further comprising:

a system fabric; and

means for transmitting the first system address over the system fabric.

12. The computer system of claim 4, wherein the first bit substitution means comprises means for storing a programmable size of the first partition identification value, and wherein the first partition identification value has the programmable size.

13. The computer system of claim 1, wherein the first one of the plurality of partitions is associated with a first partition identification value, wherein the second one of the plurality of partitions is associated with a second partition identification value, and wherein the computer system further comprises:

means for receiving a first transaction including a source terminus identifier, the source terminus identifier identifying a source device from which the incoming transaction was received;

means for identifying, based on the source terminus identifier, a third partition identification value identifying one of the first and second of the plurality of partitions;

means for transmitting at least some of the first transaction to the first hardware resource if the third partition identification value is equal to the first partition identification value; and

means for transmitting at least some of the first transaction to the second hardware resource if the third partition identification value is equal to the second partition identification value.

14. The computer system of claim 1, wherein the first and second hardware resources comprise microprocessor cores.

15. The computer system of claim 1, wherein the first and second hardware resources comprise input/output ports of an input/output controller.

16. A computer-implemented method for use in a computer system partitioned into a plurality of partitions, the computer system comprising an integrated circuit, the integrated circuit comprising a first hardware resource and a second hardware resource, the method comprising steps of:

(A) allocating the first one of the plurality of hardware resources to a first one of the plurality of hardware partitions; and

(B) allocating the second one of the plurality of hardware resources to a second one of the plurality of hardware partitions.

17. The method of claim 16, wherein the integrated circuit comprises a processor and wherein the first and second hardware resources respectively comprise a first and second processor core.

18. The method of claim 16, wherein the integrated circuit comprises an input/output controller and wherein the first and second hardware resources respectively comprise a first and second input/output port of the input/output controller.

19. The method of claim 16, wherein step (A) comprises steps of:

(A)(1) receiving from the first hardware resource a first physical address in a first address space allocated to the first one of the plurality of partitions;

(A)(2) producing a first partition-identifying address by storing, in at least part of the first physical address, a first partition identification value identifying the first one of the plurality of partitions.

20. The method of claim 19, further comprising a step of:

(A)(3) transmitting the first partition-identifying address over a system fabric.

21. The method of claim 19, wherein step (B) comprises steps of:

(B)(1) receiving from the second hardware resource a second physical address in a second address space allocated to the second one of the plurality of partitions;

(B)(2) producing a second partition-identifying address by storing, in at least part of the second physical address, a second partition identification value identifying the second one of the plurality of partitions.

22. The method of claim 21, further comprising a step of:

(B)(3) transmitting the second partition-identifying address over a system fabric.

23. The method of claim 21, wherein the first partition identification value has a first size and wherein the second partition identification value has a second size which differs from the first size.

24. The method of claim 19, wherein the step (A) further comprises a step of:

(A)(3) transmitting the first partition-identifying address to a cache.

25. The method of claim 24, wherein the step (A) further comprises a step of:

(A)(4) mapping the first physical address into a first system-address, the first system addressing including the first partition identification value.

26. The method of claim 25, wherein the step (A) further comprises a step of:

(A)(5) transmitting the first system address to a system fabric.

27. The method of claim 19, wherein the physical address comprises a used portion and an unused portion, and wherein step (A)(2) comprises a step of storing the first partition identification value in the used portion of the physical address.

28. The method of claim 16, wherein the first one of the plurality of partitions is associated with a first partition identification value, wherein the second one of the plurality of partitions is associated with a second partition identification value, and wherein step (A) comprises steps of:

(A)(1) receiving a first transaction including a source terminus identifier, the source terminus identifier identifying a source device from which the incoming transaction was received;

(A)(2) identifying, based on the source terminus identifier, a third partition identification value identifying one of the first and second of the plurality of partitions;

(A)(3) transmitting at least some of the first transaction to the first hardware resource if the third partition identification value is equal to the first partition identification value; and

(A)(4) transmitting at least some of the first transaction to the second hardware resource if the third partition identification value is equal to the second partition identification value.

29. A device for use in a partitionable computer system partitioned into a plurality of partitions, the device comprising:

partition identification means for storing a partition identification value identifying a select one of the plurality of partitions;

means for receiving a first transaction including a physical address in an address space allocated to the select one of the plurality of partitions; and

means for producing a partition-identifying address by storing the partition identification value in at least part of the physical address.

30. The device of claim 29, wherein the physical address comprises a used portion and an unused portion, and wherein the means for producing comprises means for storing the first partition identification value in the used portion of the physical address.

31. The device of claim 29, further comprising:

means for generating a modified transaction including the partition-identifying address; and

means for transmitting the modified transaction to a system fabric.

32. The device of claim 29, further comprising:

means for generating a first modified transaction including the partition-identifying address;

means for generating, based on the first modified transaction, a second modified transaction not including the partition-identifying address; and

means for transmitting the second modified transaction to a system fabric.

33. The device of claim 29, wherein the means for producing the partition-identifying address comprises means for storing a programmable size of the partition identification value, and wherein the partition identification value has the programmable size.

34. A method for use in a partitionable computer system partitioned into a plurality of partitions, the method comprising steps of:

(A) receiving a first transaction including a physical address in an address space allocated to the select one of the plurality of partitions; and

(B) producing a partition-identifying address by storing the partition identification value in at least part of the physical address.

35. The method of claim 34, wherein the physical address comprises a used portion and an unused portion, and wherein step (B) comprises a step of storing the first partition identification value in the used portion of the physical address.

36. The method of claim 34, further comprising steps of:

(C) generating a modified transaction including the partition-identifying address; and

(D) transmitting the modified transaction to a system fabric.

37. The method of claim 34, further comprising steps of:

(C) generating a first modified transaction including the partition-identifying address;

(D) generating, based on the first modified transaction, a second modified transaction not including the partition-identifying address; and

(E) transmitting the second modified transaction to a system fabric.

38. A device for use in a partitionable computer system partitioned into a plurality of partitions, the device comprising:

means for receiving a first transaction including a physical address in an address space allocated to the select one of the plurality of partitions; and

means for producing a partition-identifying address by storing the partition identification value in at least part of the physical address.

39. The device of claim 38, wherein the physical address comprises a used portion and an unused portion, and wherein the means for producing comprises means for storing the first partition identification value in the used portion of the physical address.

40. The device of claim 38, further comprising:

means for generating a modified transaction including the partition-identifying address; and

means for transmitting the modified transaction to a system fabric.

41. The device of claim 38, further comprising:

means for generating a first modified transaction including the partition-identifying address;

means for generating, based on the first modified transaction, a second modified transaction not including the partition-identifying address; and

means for transmitting the second modified transaction to a system fabric.

42. A device for use in a partitionable computer system partitioned into a plurality of partitions, wherein a first one of the plurality of partitions is associated with a first partition identification value, wherein a second one of the plurality of partitions is associated with a second partition identification value, the device comprising:

means for receiving a transaction including a source terminus identifier, the source terminus identifier identifying a source device from which the incoming transaction was received;

means for identifying, based on the source terminus identifier, a third partition identification value identifying one of the first and second of the plurality of partitions;

means for transmitting at least some of the transaction to a first hardware resource allocated to the first one of the plurality of partitions if the third partition identification value is equal to the first partition identification value; and

means for transmitting at least some of the transaction to a second hardware resource allocated to the second one of the plurality of partitions if the third partition identification value is equal to the second partition identification value.

43. A method for use in a partitionable computer system partitioned into a plurality of partitions, wherein a first one of the plurality of partitions is associated with a first partition identification value, wherein a second one of the plurality of partitions is associated with a second partition identification value, the method comprising steps of:

(A) receiving a transaction including a source terminus identifier, the source terminus identifier identifying a source device from which the incoming transaction was received;

(B) identifying, based on the source terminus identifier, a third partition identification value identifying one of the first and second of the plurality of partitions;

(C) transmitting at least some of the transaction to a first hardware resource allocated to the first one of the plurality of partitions if the third partition identification value is equal to the first partition identification value; and

(D) transmitting at least some of the transaction to a second hardware resource allocated to the second one of the plurality of partitions if the third partition identification value is equal to the second partition identification value.

44. A device for use in a partitionable computer system partitioned into a plurality of partitions, wherein a first one of the plurality of partitions is associated with a first partition identification value, wherein a second one of the plurality of partitions is associated with a second partition identification value, the device comprising:

means for receiving a transaction including a source terminus identifier, the source terminus identifier identifying a source device from which the incoming transaction was received;

means for identifying, based on the source terminus identifier, a third partition identification value identifying one of the first and second of the plurality of partitions;

means for transmitting at least some of the transaction to a first hardware resource allocated to the first one of the plurality of partitions if the third partition identification value is equal to the first partition identification value; and

means for transmitting at least some of the transaction to a second hardware resource allocated to the second one of the plurality of partitions if the third partition identification value is equal to the second partition identification value.