Timing vector program mechanism
First Claim
1. A method of controlling operation execution in a system comprising:
- defining a time reference;
defining a plurality of timing vectors each of which is associated with at least one operation;
associating a time associated with the time reference with each timing vector;
comparing the time reference with each time associated with each timing vector to identify a matching timing vector; and
performing the at least one operation associated with the matching timing vector.
6 Assignments
0 Petitions
Accused Products
Abstract
Timing vectors are used to pass execution of time-dependent operations from firmware/software to a hardware component (e.g., a state machine). These vectors may be stored as a vector table in a data memory that is accessible by both the firmware/software and the hardware component. Based on the processing being performed in the system, the firmware/software will determine that one or more operations will need to be performed at a certain time. The firmware/software stores a reference to that time and a reference to the operation(s) in a vector. The hardware component continually monitors time in the system. In addition, the hardware component will monitor each vector to determine whether the current time matches the time associated with a given vector. When there is match, the hardware component causes the operation(s) associated with the vector to be performed. The system also may perform different operations at a given time depending on the operating condition (e.g., state) of the system.
7 Citations
37 Claims
-
1. A method of controlling operation execution in a system comprising:
-
defining a time reference;
defining a plurality of timing vectors each of which is associated with at least one operation;
associating a time associated with the time reference with each timing vector;
comparing the time reference with each time associated with each timing vector to identify a matching timing vector; and
performing the at least one operation associated with the matching timing vector. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
-
-
21. An apparatus for controlling operation execution in a system comprising:
-
at least one data memory;
at least one processor configured to execute firmware for defining a time reference, defining a plurality of timing vectors each of which is associated with at least one operation, associating a time associated with the time reference with each timing vector, and storing the timing vectors in the data memory; and
at least one hardware state machine configured to compare the time reference with each time associated with each timing vector to identify a matching timing vector and initiate execution of the at least one operation associated with the matching timing vector. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37)
-
Specification
-
- Resources
-
Current AssigneeAvago Technologies International Sales Pte Limited (Broadcom, Inc.)
-
Original AssigneeBroadcom Corporation (Broadcom, Inc.)
-
InventorsZhuang, Yuan, Wong, Yuqian C.
-
Granted Patent
-
Time in Patent OfficeDays
-
Field of Search
-
US Class Current713/400
-
CPC Class CodesG04G 15/006 for operating at a number o...G06F 9/4825 Interrupt from clock, e.g. ...H04L 7/10 Arrangements for initial sy...Y02D 10/00 Energy efficient computing,...
