Method and system of servicing asynchronous interrupts in multiple processors executing a user program

• US 20060020852A1
• Filed: 01/25/2005
• Published: 01/26/2006
• Est. Priority Date: 03/30/2004
• Status: Abandoned Application

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Garcia, David J., Bruckert, William F., Jardine, Robert L., Klecka, James S., Bernick, David L., Rector, Russell M.
• Application Number:
  US11/042,429
• Publication Number:
  US 20060020852A1
• Time in Patent Office: Days
• US Class Current: 714/11
• CPC Class Codes: G06F 11/1641 where the comparison is not performed by the redundant processing components
• CPC Class Codes: G06F 11/1687 at event level, e.g. by interrupt or result of polling
• CPC Class Codes: G06F 11/183 by voting, the voting not being performed by the redundant components
• CPC Class Codes: G06F 13/26 with priority control

Abstract

A method and system of servicing asynchronous interrupts in multiple processors executing a user program. Some of the exemplary embodiments may be a method comprising executing a user program on a first processor and a duplicate copy of the user program on a second processor, receiving an asynchronous interrupt by both the first and second processors, executing an interrupt service routine on the first processor at an agreed system call of the user program executed on the first processor, and executing an interrupt service routine on the second processor at the agreed system call of the user program executed on the second processor.

Claims

1. A processor-based method comprising:

executing a user program on a first processor, and a duplicate copy of the user program on a second processor;

receiving an asynchronous interrupt by both the first and second processors;

executing an interrupt service routine on the first processor at an agreed system call of the user program executed on the first processor; and

executing an interrupt service routine on the second processor at the agreed system call of the user program executed on the second processor.

2. The processor-based method as defined in claim 1 further comprising:

executing a duplicate copy of the user program on a third processor;

receiving the asynchronous interrupt by the processors; and

executing an interrupt service routine on the third processor at the agreed system call of the user program executed on the third processor.

3. The processor-based method as defined in claim 1 further comprising:

exchanging between the processors an interrupt identification and a proposed system call number at which to service the interrupt;

checking the exchanged interrupt identifications to determine if the interrupts identified match; and

executing the interrupt service routine at the agreed system call being the highest proposed system call number, the executing the interrupt service routine if the exchanged interrupt identifications match.

4. The processor-based method as defined in claim 3 further comprising between exchanging and checking, continuing to execute the user program in each processor.

5. The processor-based method as defined in claim 3 further comprising:

exchanging between the processors a plurality of interrupt identifications and a plurality of proposed system call number, one each for each of the plurality of interrupt identifications;

checking the exchanged interrupt identifications to determine if the interrupts identified match; and

if any one or more of the exchanged interrupt identifications match

executing interrupt service routines at the agreed system call being the highest proposed system call number.

6. The processor-based method as defined in claim 3 wherein exchanging further comprises:

writing, by the first processor, the interrupt identification and proposed system call number to registers of a logic system coupling the first and second processors;

writing, by the second processor, the interrupt identification and proposed system call number to the registers of the logic device; and

providing to each processor by the logic system at least a portion of the information in the registers.

7. The processor-based method as defined in claim 6 further comprising, between the writing and providing:

continuing to execute the user program in the first processor until user program reaches the proposed system call number; and

then

stalling the first processor at least until the providing a portion of the information.

8. The processor-based method as defined in claim 1 wherein exchanging further comprises:

writing, by the first processor, the interrupt identification and proposed system call number to registers of a logic system coupling the first and second processors;

writing, by the second processor, the interrupt identification and proposed system call number to the registers of the logic device;

reading by the first processor the interrupt identification and proposed system call number of the second processor; and

reading by the second processor the interrupt identification and proposed system call number of the first processor.

9. The processor-based method as defined in claim 1 wherein between the receiving and executing the interrupt service routine, continuing to execute the user program in each processor.

10. A computing system comprising:

a first processor operable to execute a user program; and

a second processor coupled to the first processor, the second processor operable to execute a duplicate copy of the user program;

wherein the first processor is operable to provide information to the second processor indicating an interrupt has been asserted and a proposed system call number of the user program at which to service the interrupt;

wherein the second processor is operable to provide information to the first processor indicating an interrupt has been asserted and a proposed system call number of the user program at which to service the interrupt;

wherein at an agreed system call number of the respective user programs, each of the first and second processors are operable to service the interrupt.

11. The computing system as defined in claim 10 further comprising:

wherein the first processor is operable to provide information to the second processor indicating that a plurality of interrupts have been asserted, and wherein the first processor is also operable to provide a plurality of proposed system call numbers, one each for each of the plurality of interrupts;

wherein the second processor is operable to provide information to the first processor indicating that a plurality of interrupts have been asserted, and wherein the second processor is also operable to provide a plurality of proposed system call numbers, one each for each of the plurality of interrupts; and

wherein at an agreed system call number of the respective user programs, each of the first and second processors are operable to service at least one interrupt.

12. The computing system as defined in claim 10 further comprising:

a synchronization logic having a register set, the synchronization logic coupling the first and second processors;

wherein the information provided by the first processor is written to at least a portion of the register set; and

wherein the information provided by the second processor is written to at least a portion of the register set.

13. The computing system as defined in claim 12 wherein after writing of information to the register set by the first and second processors, the synchronization logic is operable to write at least a portion of the information to memory of each processor.

14. The computer system as defined in claim 13 wherein the synchronization logic is operable to write all the information of the register set to memory of each processor.

15. The computing system as defined in claim 12 wherein the first processor is operable to read at least some of the information from the register set, and wherein the second processor is operable to read at least some of the information from the register set.

16. The computer system as defined in claim 12 wherein after the information provided by each processor is written to the register set, the user program in each processor is operable to resume execution.

17. A computer readable media storing an interrupt handler routine that, when executed, performs a method comprising:

selecting a highest priority interrupt; and

providing an interrupt identifier and a proposed system call number at which to service the interrupt to a different processor than executes the current instance of the interrupt handler routine.

18. The computer readable media as defined in claim 17 wherein selecting further comprises:

reading a pending interrupt list; and

selecting the highest priority interrupt.

19. The computer readable media as defined in claim 18 further comprising moving the interrupt identifier and proposed system call number to a log.

20. The computer readable media as defined in claim 18 further comprising leaving the interrupt identifier on the pending interrupt list, and setting a flag to indicate that the providing has taken place.

21. The computer readable media as defined in claim 18 further comprising:

selecting a plurality of interrupts from the pending list; and

providing a plurality of interrupt identifiers, one each for each interrupt selected, and also providing a plurality of proposed system call numbers, one each for each interrupt selected.

22. The computer readable media as defined in claim 17 wherein providing further comprises writing the interrupt identifier and proposed system call number to a register set in a logic system coupling the processor that executes the current instance of the interrupt handler routine and the different processor.

23. The computer readable media as defined in claim 17 wherein after the writing the method further comprises resuming execution of the user program that was executing prior to assertion of the interrupt.

24. A computer readable media storing a system call program that, when executed, performs a method comprising:

determining whether there is agreement of a plurality of processors to service a particular interrupt; and

scheduling an interrupt service routine if there is agreement to service the particular interrupt and if the current system call number is equal to at least one of the system call numbers proposed by at least one of the plurality of processors.

25. The computer readable media as defined in claim 24 wherein determining further comprises

reading a log holding an interrupt identifier and a system call number previously proposed;

reading a memory location to which an interrupt identifier and proposed system call number from at least one other processor has been written; and

verifying whether all processors agree to servicing the particular interrupt.

26. The computer readable media as defined in claim 25 wherein scheduling further comprises scheduling the interrupt service routine if the current system call number is equal to the highest system call number proposed by any of the processors.

27. The computer readable media as defined in claim 26 wherein the determining further comprises writing the particular interrupt and the highest proposed system call number to a confirmed list if the highest proposed system call number is different than the current system call number.

28. The computer readable media as defined in claim 24 wherein determining further comprises

reading a memory location to which an interrupt identifier and proposed system call number from at least one other processor has been written;

and

verifying whether all processors agree to servicing the particular interrupt.

29. The computer readable media as defined in claim 28 wherein scheduling further comprises scheduling the interrupt service routine if the current system call number is equal to the highest system call number proposed by any of the processors.

30. The computer readable media as defined in claim 29 wherein the determining further comprises writing the particular interrupt and the highest proposed system call number to a confirmed list if the highest proposed system call number is different than the current system call number.

31. The computer readable media as defined in claim 24 wherein the method further comprises scheduling an interrupt service routine to service a particular interrupt from a previous executing of the system call program if the current system call number is the same as the highest proposed system call number from the previous execution.

32. The computer readable media as defined in claim 24 wherein the method further comprises, after the determining:

selecting a highest priority interrupt;

reading the current system call number; and

providing an interrupt identifier and a proposed system call number at which to service the interrupt to each of the plurality of processors.

33. The computer readable media as defined in claim 32 further comprising writing the interrupt identifier and proposed system call number to a pending rendezvous log.

34. The computer readable media as defined in claim 32 wherein selecting further comprises:

reading a pending interrupt list; and

selecting the highest priority interrupt from the pending interrupt list.

35. The computer readable media as defined in claim 34 further comprising:

selecting a plurality of interrupts from the pending interrupt list; and

providing a plurality of interrupt identifiers, one each for each interrupt selected, and also providing a plurality of proposed system call numbers, one each for each interrupt.

36. The computer readable media as defined in claim 32 wherein providing further comprises writing the interrupt identifier and proposed system call number to a register set in a logic system coupling the plurality of processors.