Automatic analog test & compensation with built-in pattern generator & analyzer
First Claim
1. A linearity measurement circuit, comprising:
- a. a test pattern generator for generating a first sine wave pattern, a second sine wave pattern, and a third sine wave pattern, each sine wave pattern in the form of a digital signal, wherein the first sine wave pattern and the second sine wave pattern are summed by an adder and supplied to a D-A converter and an analog circuit under test;
b. an A-D converter operative to convert an analog signal outputted from the analog circuit under test to a digital output signal; and
c. an output response analyzer including a first multiplier and accumulator pair for multiplying and accumulating the digital output signal and the second sine wave pattern to generate a first signal power, and a second multiplier and accumulator pair for multiplying and accumulating the digital output signal and the third sine wave pattern to generate a second signal power.
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Accused Products
Abstract
A built-in-self test (BIST) scheme for analog circuitry functionality tests such as frequency response, gain, cut-off frequency, signal-to-noise ratio, and linearity measurement. The BIST scheme utilizes a built-in direct digital synthesizer (DDS) as the test pattern generator that can generate various test waveforms such as chirp, ramp, step frequency, two-tone frequencies, sweep frequencies, MSK, phase modulation, amplitude modulation, QAM and other hybrid modulations. The BIST scheme utilizes a multiplier followed by an accumulator as the output response analyzer (ORA). The multiplier extracts the spectrum information at the desired frequency without using Fast Fourier Transform (FFT) and the accumulator picks up the DC component by averaging the multiplier output.
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Citations
42 Claims
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1. A linearity measurement circuit, comprising:
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a. a test pattern generator for generating a first sine wave pattern, a second sine wave pattern, and a third sine wave pattern, each sine wave pattern in the form of a digital signal, wherein the first sine wave pattern and the second sine wave pattern are summed by an adder and supplied to a D-A converter and an analog circuit under test;
b. an A-D converter operative to convert an analog signal outputted from the analog circuit under test to a digital output signal; and
c. an output response analyzer including a first multiplier and accumulator pair for multiplying and accumulating the digital output signal and the second sine wave pattern to generate a first signal power, and a second multiplier and accumulator pair for multiplying and accumulating the digital output signal and the third sine wave pattern to generate a second signal power. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A phase and gain measurement circuit, comprising:
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a. a test pattern generator for generating a sine wave pattern and a cosine wave pattern, each wave pattern in the form of a digital signal, and supplying the sine wave pattern to a D-A converter and an analog circuit under test;
b. an A-D converter operative to convert an analog signal outputted from the analog circuit under test to a digital output signal; and
c. an output response analyzer including a first multiplier and accumulator pair for multiplying and accumulating the digital output signal and the sine wave pattern to generate a first signal power and a second multiplier and accumulator pair for multiplying and accumulating the digital output signal and the cosine wave pattern to generate a second signal power. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28)
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29. A signal-to-noise measurement circuit, comprising:
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a. a test pattern generator for generating a first sine wave pattern, a second sine wave pattern, and a cosine wave pattern, each sine wave pattern in the form of a digital signal, wherein the first sine wave pattern is supplied to a D-A converter and an analog circuit under test;
b. an A-D converter operative to convert an analog signal outputted from the analog circuit under test to a digital output signal; and
c. an output response analyzer including a first multiplier and accumulator pair for multiplying and accumulating the digital output signal and the second sine wave pattern to generate a first signal power, and a second multiplier and accumulator pair for multiplying and accumulating the digital output signal and the cosine wave pattern to generate a second signal power. - View Dependent Claims (30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41)
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42. A built-in self test (BIST) architecture for an analog circuit functionality test, the BIST architecture comprising:
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a. a direct digital synthesizer (DDS) configured to generate a test waveform;
b. a D-A converter configured to receive and convert the test waveform to an analog signal, wherein the analog signal is an input signal for a device under test;
c. an A-D converter configured to receive an output from the device under test, and further configured to convert the output to a digital signal; and
d. an output response analyzer (ORA), wherein the ORA includes;
i. a multiplier configured to receive the digital signal and the test waveform, and further configured to extract a set of spectrum information at a desired frequency; and
ii. an accumulator coupled to the multiplier, wherein the accumulator is configured to average an output of the multiplier, wherein the test waveform is generated over a number of clock cycles and the accumulator collects the output from the analog circuit.
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Specification