Barrier regions for image sensors

• US 20060022231A1
• Filed: 07/19/2005
• Published: 02/02/2006
• Est. Priority Date: 02/02/2004
• Status: Active Grant

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Inventors: Mauritzson, Richard A., Quinlin, William T., Rhodes, Howard E.
• Granted Patent: US 7,902,624 B2
• Time in Patent Office: Days
• US Class Current: 257/291
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14607 Geometry of the photosensitive area
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/1463 Pixel isolation structures
• CPC Class Codes: H01L 27/14645 Colour imagers
• CPC Class Codes: H01L 27/14654 Blooming suppression
• CPC Class Codes: H01L 27/14689 MOS based technologies

Abstract

Embodiments of the invention provide an image sensor that includes a barrier region for isolating devices. The image sensor comprises a substrate and an array of pixel cells formed on the substrate. Each pixel cell comprises a photo-conversion device. The array comprises a first pixel cell having a first configuration, a second pixel cell having a second configuration, and at least one barrier region formed between the first and second pixel cells for capturing and removing charge. The barrier region comprises a charge accumulation region of a particular conductivity type in a substrate electrically connected to a voltage source terminal. The charge accumulation region accumulates charge and prevents charge transference from a pixel cell or peripheral circuitry on one side of the barrier region to a pixel cell on another side of the barrier region.

Claims

1. An image sensor comprising:

a substrate;

an array of pixel cells formed on the substrate, each pixel cell comprising a photo-conversion device, the array comprising a first pixel cell having a first configuration and a second pixel cell having a second configuration; and

at least one barrier region for capturing and removing charge, the at least one barrier region comprising a charge accumulation region of a particular conductivity type electrically connected to a voltage source terminal.

2. The image sensor of claim 1, wherein the conductivity type of the charge accumulation region is n-type, and wherein the voltage source terminal is a positive voltage terminal.

3. The image sensor of claim 1, wherein the charge accumulation region has an n-type implant dose within the range of approximately 5×

10¹¹ to approximately 1×

10¹⁴ atoms/cm².

4. The image sensor of claim 1, wherein the charge accumulation region has an n-type implant dose within the range of approximately 2×

10¹² atoms/cm² to approximately 1×

10¹⁴ atoms/cm².

5. The image sensor of claim 1, wherein the charge accumulation region has an n-type implant dose greater than approximately 1×

10¹⁴ atoms/cm².

6. The image sensor of claim 1, wherein the conductivity type of the charge accumulation region is p-type, and wherein the voltage source terminal is a ground voltage.

7. The image sensor of claim 1, wherein the charge accumulation region is connected to a voltage source terminal using a contact and metal.

8. The image sensor of claim 7, wherein the barrier region further comprises a contact region of the particular conductivity type below the contact.

9. The image sensor of claim 8, wherein the contact region has an n-type implant dose greater than approximately 1×

10¹⁴ atoms/cm².

10. The image sensor of claim 1, further comprising at least one wiring layer for routing electrical signals over the barrier region.

11. The image sensor of claim 1, further comprising a plurality of wiring layers for routing electrical signals over the barrier region, wherein the plurality of wiring layers are not parallel to each other.

12. The image sensor of claim 1, wherein the barrier region is between the first and second pixel cells.

13. The image sensor of claim 1, further comprising at least one wiring layer for routing electrical signals over the first and second pixel cells and located such that the at least one wiring layer does not block light from reaching the respective photo-conversion devices.

14. The image sensor of claim 13, wherein the at least one wiring layer is located over the first pixel cell, the at least one barrier region, and the second pixel cell.

15. The image sensor of claim 13, wherein the charge accumulation region is an np diode.

16. The image sensor of claim 1, wherein the charge accumulation region is a pnp diode.

17. The image sensor of claim 1, wherein the at least one barrier region is configured as at least a portion of a pixel cell in the array.

18. The image sensor of claim 1, wherein the at least one barrier region is configured as a group of pixel cells in the array, and wherein the charge accumulation region is continuous.

19. The image sensor of claim 18, wherein the barrier region is configured as a row of pixel cells in the array.

20. The image sensor of claim 18, wherein the barrier region is configured as a column of pixel cells in the array.

21. The image sensor of claim 1, wherein the at least one barrier region further comprises at least one transistor.

22. The image sensor of claim 1, wherein the image sensor is a CMOS image sensor.

23. The image sensor of claim 1, wherein the image sensor is a CCD image sensor.

24. A processor system, comprising:

(i) a processor; and

(ii) an image sensor coupled to the processor, the image sensor comprising;

a substrate;

an array of pixel cells formed on the substrate, each pixel cell comprising a photo-conversion device, the array comprising a first pixel cell having a first configuration and a second pixel cell having a second configuration; and

at least one barrier region formed between the first and second pixel cells for capturing and removing charge, the at least one barrier region comprising a charge accumulation region of a particular conductivity type electrically connected to a voltage source terminal.

25. The processor system of claim 24, wherein the image sensor is a CMOS image sensor.

26. The processor system of claim 24, wherein the image sensor is a CCD image sensor.

27. The processor system of claim 24, further comprising at least one wiring layer for routing electrical signals over the first pixel cell, the second pixel cell, and the at least one barrier region and located such that the at least one wiring layer does not block light from reaching the respective photo-conversion devices.

28. A method of forming an image sensor, the method comprising:

providing a substrate;

providing an array of pixel cells on the substrate, the array comprising a first pixel cell having a first configuration and a second pixel cell having a second configuration; and

forming at least one barrier region adjacent to at least one pixel cell by forming a charge accumulation region of a particular conductivity type on the substrate and electrically connecting the charge accumulation region to a voltage source terminal.

29. The method of claim 28, wherein the act of forming the charge accumulation region comprises forming an np diode.

30. The method of claim 28, wherein the act of forming the charge accumulation region comprises forming a pnp diode.

31. The method of claim 28, wherein the act of forming the charge accumulation region comprises forming the charge accumulation region with n-type conductivity, and wherein the act of electrically connecting the charge accumulation region comprises electrically connecting the charge accumulation region to a positive voltage source terminal.

32. The method of claim 31, wherein the act of forming the charge accumulation region comprises forming the charge accumulation region using an n-type implant dose within the range of approximately 5×

10¹¹ to approximately 1×

10¹⁴ atoms/cm².

33. The method of claim 31, wherein the act of forming the charge accumulation region comprises forming the charge accumulation region using an n-type implant dose within the range of approximately 2×

10¹² atoms/cm² to approximately 1×

10¹⁴ atoms/cm².

34. The method of claim 31, wherein the act of forming the charge accumulation region comprises forming the charge accumulation region using an n-type implant dose greater than approximately 1×

10¹⁴ atoms/cm².

35. The method of claim 28, wherein the act of forming the charge accumulation region comprises forming the charge accumulation region with p-type conductivity, and wherein the act of electrically connecting the charge accumulation region comprises electrically connecting the charge accumulation region to a ground voltage source terminal.

36. The method of claim 28, wherein the act of connecting the charge accumulation region to a voltage source terminal comprises forming a contact and a metal connection.

37. The method of claim 36, wherein the act of forming the barrier region comprises forming the contact region of the particular conductivity type below the contact.

38. The method of claim 37, wherein the act of forming the contact region comprises forming the contact region using an n-type implant dose greater than approximately 1×

10¹⁴ atoms/cm².

39. The method of claim 28, further comprising forming at least one wiring layer for routing electrical signals over the barrier region.

40. The method of claim 28, further comprising forming a plurality of wiring layers for routing electrical signals over the barrier region, the plurality of wiring layers not formed parallel to each other.

41. The method of claim 28, wherein the at least one barrier region is between the first and second pixel cells.

42. The method of claim 41, further comprising forming at least one wiring layer for routing electrical signals over the first and second pixel cells such that the at least one wiring layer does not block light from reaching the respective photo-conversion devices.

43. The method of claim 42, wherein the act of forming the at least one wiring layer comprises forming the at least one wiring layer over the first pixel cell, the at least one barrier region, and the second pixel cell.

44. The method of claim 28, further comprising forming a plurality of barrier regions.

45. The method of claim 28, wherein the act of forming the at least one barrier region comprises forming the at least one barrier region as at least a portion of a pixel cell in the array.

46. The method of claim 28, wherein the act of forming the at least one barrier region comprises forming the at least one barrier region as a group of pixel cells in the array and forming a continuous charge accumulation region.

47. The method of claim 46, wherein the act of forming the at least one barrier region comprises forming the at least one barrier region as a row of pixel cells.

48. The method of claim 46, wherein the act of forming the at least one barrier region comprises forming the at least one barrier region as a column of pixel cells.

49. The method of claim 28, wherein the act of forming the at least one barrier region further comprises forming at least one transistor.