CMOS imager with selectively silicided gates
First Claim
Patent Images
1. A CMOS imager having improved transistor speed comprising:
- a substrate;
an array of pixel cells formed on said substrate, each of said cells including a photocollection region and at least one transistor wherein said transistor includes an opaque conductive layer deposited over the gate region of said transistor; and
signal processing circuitry on said substrate, wherein said circuitry is connected to said array.
1 Assignment
0 Petitions
Accused Products
Abstract
The invention also relates to an apparatus and method for selectively providing a silicide coating over the transistor gates of a CMOS imager to improve the speed of the transistor gates. The method further includes an apparatus and method for forming a self aligned photo shield over the CMOS imager.
-
Citations
2 Claims
-
1. A CMOS imager having improved transistor speed comprising:
-
a substrate;
an array of pixel cells formed on said substrate, each of said cells including a photocollection region and at least one transistor wherein said transistor includes an opaque conductive layer deposited over the gate region of said transistor; and
signal processing circuitry on said substrate, wherein said circuitry is connected to said array.
-
-
2-86. -86. (canceled)
Specification