CMOS imager with selectively silicided gates

• US 20060022233A1
• Filed: 03/14/2005
• Published: 02/02/2006
• Est. Priority Date: 08/16/1999
• Status: Active Grant

• Current Assignee: Round Rock Research LLC
• Original Assignee: Howard E. Rhodes
• Inventors: Rhodes, Howard E.
• Granted Patent: US 7,348,613 B2
• Time in Patent Office: Days
• US Class Current: 257/292
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/1462 Coatings
• CPC Class Codes: H01L 27/14623 Optical shielding
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14687 Wafer level processing
• CPC Class Codes: H01L 27/14689 MOS based technologies

Abstract

The invention also relates to an apparatus and method for selectively providing a silicide coating over the transistor gates of a CMOS imager to improve the speed of the transistor gates. The method further includes an apparatus and method for forming a self aligned photo shield over the CMOS imager.

Claims

1. A CMOS imager having improved transistor speed comprising:

a substrate;

an array of pixel cells formed on said substrate, each of said cells including a photocollection region and at least one transistor wherein said transistor includes an opaque conductive layer deposited over the gate region of said transistor; and

signal processing circuitry on said substrate, wherein said circuitry is connected to said array.

2-86. -86. (canceled)