Transparent amorphous carbon structure in semiconductor devices

• US 20060022247A1
• Filed: 08/30/2005
• Published: 02/02/2006
• Est. Priority Date: 09/12/2003
• Status: Abandoned Application

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Yin, Zhiping, Li, Weimin
• Application Number:
  US11/215,614
• Publication Number:
  US 20060022247A1
• Time in Patent Office: Days
• US Class Current: 257/296
• CPC Class Codes: H01L 21/02115 the material being carbon, e.g. alpha-C, diamond or hydrogen doped carbon
• CPC Class Codes: H01L 21/02126 the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
• CPC Class Codes: H01L 21/0214 the material being a silicon oxynitride, e.g. SiON or SiON:H
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/0237 Materials
• CPC Class Codes: H01L 21/02439 Materials
• CPC Class Codes: H01L 21/02505 consisting of more than two layers
• CPC Class Codes: H01L 21/02527 Carbon, e.g. diamond-like carbon
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/0332 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/3081 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/3146 Carbon layers, e.g. diamond-like layers
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor

Abstract

A transparent amorphous carbon layer is formed. The transparent amorphous carbon layer has a low absorption coefficient such that the amorphous carbon is transparent in visible light. The transparent amorphous carbon layer may be used in semiconductor devices for different purposes. The transparent amorphous carbon layer may be included in a final structure in semiconductor devices. The transparent amorphous carbon layer may also be used as a mask in an etching process during fabrication of semiconductor devices.

Claims

1. A memory device comprising:

a substrate having a plurality of doped regions;

a plurality of gate structures over the substrate;

an insulating layer over the gate structures;

a plurality of contacts, each of the contacts being located between two gate structures, each of the contacts extending through the insulating layer and contacting one of the doped regions; and

an amorphous carbon layer over the substrate, wherein the amorphous carbon layer is transparent in visible light range.

2. The memory device of claim 1, wherein the insulating layer includes a glass layer.

3. The memory device of claim 2, wherein one of the gate structures and a pair of doped regions of the plurality of doped regions are parts of a transistor.

4. The memory device of claim 3, wherein a first doped region of the pair of doped regions is a part of a capacitor plate.

5. The memory device of claim 4, wherein a second doped region of the pair of doped regions is coupled to a bit line via one of the contacts.

6. A memory device comprising:

a substrate having a plurality of doped regions;

a plurality of gate structures over the substrate;

a glass layer over the gate structures;

a barrier layer between the gate structures and the glass layer for preventing cross-diffusion between the gate structures and the glass layer;

a plurality of contacts, each of the contacts being located between two gate structures and contacting one of the doped regions; and

an amorphous carbon layer over substrate, wherein the amorphous carbon layer is transparent in visible light range.

7. The memory device of claim 6, wherein one of the gate structures and a pair of doped regions of the plurality of doped regions are parts of a transistor.

8. The memory device of claim 7, wherein a first doped region of the pair of doped regions is a part of a capacitor plate.

9. The memory device of claim 8, wherein a second doped region of the pair of doped regions is coupled to a bit line via one of the contacts.

10. The memory device of claim 6 further comprising an oxide layer formed directly over the amorphous carbon layer.

11. The memory device of claim 10 further comprising a photoresist layer formed directly over the oxide layer.

12. The memory device of claim 11, wherein the photoresist layer includes at least one opening.

13. The memory device of claim 12, wherein the oxide layer includes at least one opening continuous with the opening of the photoresist layer.

14. The memory device of claim 13, wherein the amorphous carbon layer includes at least one opening continuous with the opening of the oxide layer.

15. A memory device comprising:

a substrate having at least one alignment mark;

a device structure over the substrate; and

an amorphous carbon layer over the substrate, wherein the amorphous carbon layer is transparent in visible light range for improving a reading of the alignment mark.

16. The memory device of claim 15, wherein the second amorphous carbon layer has a thickness greater than 4000 Angstroms for etching the device structure without substantially affecting the reading of the alignment mark.

17. The memory device of claim 15, wherein the substrate includes a plurality of doped regions, and wherein the device structure includes a plurality of gate structures, a plurality of contacts, each of the contacts being located between two gate structures and contacting one of the doped regions.

18. The memory device of claim 17 further comprising an oxide layer over the amorphous carbon layer.

19. The memory device of claim 18 further comprising a photoresist layer over the oxide layer.

20. The memory device of claim 19 further comprising an antireflective layer between the oxide layer and the photoresist layer.

21. The memory device of claim 19 wherein the photoresist layer includes at least one opening, wherein the oxide layer includes at least one opening continuous with the opening of the photoresist layer.

22. The memory device of claim 21, wherein the amorphous carbon layer includes at least one opening continuous with the opening of the oxide layer and the opening of the photoresist layer.

23. A memory device comprising:

a substrate having a plurality of doped regions;

device structure formed over the substrate, the device structure including a plurality of gate structures, a plurality of contacts, each of the contacts being located between two gate structures and contacting one of the doped regions, and an insulating layer formed over the gate structures and the contacts; and

a masking structure formed over the device structure, the masking structure including an amorphous carbon layer, wherein the amorphous carbon layer is transparent in visible light range.

24. The memory device of claim 23, wherein the amorphous carbon layer has a thickness of at least 4000 Angstroms.

25. The memory device of claim 24, wherein the device structure has a thickness of at least 40000 Angstroms.

26. The memory device of claim 23, wherein the masking structure further includes a silicon oxynitride layer over the amorphous carbon layer.

27. The memory device of claim 23, wherein the masking structure further includes a photoresist layer over the amorphous carbon layer.

28. The memory device of claim 27, wherein the masking structure further includes an antireflective layer over the amorphous carbon layer.

29. The memory device of claim 27, wherein the photoresist layer includes at least one opening.

30. The memory device of claim 29, wherein the amorphous carbon layer includes at least one opening continuous with the opening of the photoresist layer.

31. The memory device of claim 30, wherein the insulating layer includes at least one opening continuous with both of the opening of the amorphous carbon layer and the opening of the photoresist layer.

32. The memory device of claim 23, wherein the device structure further includes a barrier layer located between the gate structures and the contacts.

33. The memory device of claim 23, wherein the amorphous carbon layer has an absorption coefficient between about 0.15 and about 0.001 at wavelength of 633 nanometers.

34. A memory device comprising:

a substrate having at least one alignment mark, and a plurality of doped regions;

a plurality of gate structures over the substrate, at least one of the gate structures including a first amorphous carbon layer;

a plurality of contacts, each of the contacts being located between two gate structures and contacting one of the doped regions; and

a second amorphous carbon layer over the device structure, wherein the second amorphous carbon layer is transparent in visible light range for improving a reading of the alignment mark.

35. The memory device of claim 34 further comprising a hydrogenated silicon oxide over the second amorphous carbon layer.

36. The memory device of claim 34 further comprising a photoresist layer over the hydrogenated silicon oxide layer.

37. The memory device of claim 36 further comprising an antireflective layer between the hydrogenated silicon oxide layer and the photoresist layer.

38. The memory device of claim 37 further comprising an antireflective layer between the hydrogenated silicon oxide layer and the photoresist layer.

39. The memory device of claim 37, wherein the photoresist layer includes at least one opening, wherein the hydrogenated silicon oxide layer includes at least one opening continuous with the opening of the photoresist layer, and wherein the second amorphous carbon layer includes at least one opening continuous with the opening of the hydrogenated silicon oxide layer.

40. A memory device comprising:

a substrate having at least one alignment mark, and a plurality of doped regions;

a plurality of gate structures over the substrate, at least one of the gate structures including a first amorphous carbon layer;

an insulating layer over the gate structures;

a barrier layer between the gate structures and the insulating layer for preventing cross-diffusion between the gate structures and the insulating layer;

a plurality of contacts, each of the contacts being located between two gate structures and contacting one of the doped regions; and

a second amorphous carbon layer over the device structure, wherein the second amorphous carbon layer is transparent in visible light range for improving a reading of the alignment mark.

41. The memory device of claim 40 further comprising a hydrogenated silicon oxynitride over the second amorphous carbon layer.

42. The memory device of claim 41 further comprising a photoresist layer over the hydrogenated silicon oxynitride layer.

43. The memory device of claim 42 further comprising an antireflective layer between the hydrogenated silicon oxynitride layer and the photoresist layer.

44. The memory device of claim 42, wherein the photoresist layer includes at least one opening, wherein the hydrogenated silicon oxynitride layer includes at least one opening continuous with the opening of the photoresist layer, and wherein the second amorphous carbon layer includes at least one opening continuous with the opening of the hydrogenated silicon oxynitride layer.