Memory device and method for fabricating the same

• US 20060022249A1
• Filed: 02/07/2005
• Published: 02/02/2006
• Est. Priority Date: 07/27/2004
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Park, Hyung-Soon, Yang, Hong-Seon, Jang, Se-Aug, Jung, Tae-Woo, Sohn, Hyun-Chul, Kim, Woo-Jin, Hwang, Eung-Rim, Kim, Young-Bog, Kim, Seo-Min
• Granted Patent: US 7,045,846 B2
• Time in Patent Office: Days
• US Class Current: 257/306
• CPC Class Codes: H01L 29/7886 Hot carrier produced by avalanche breakdown of a PN junction, e.g. FAMOS
• CPC Class Codes: H10B 12/0335 Making a connection between the transistor and the capacitor, e.g. plug
• CPC Class Codes: H10B 12/485 Bit line contacts
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Disclosed are a memory device and a method for fabricating the same. The memory device includes: a substrate provided with a trench; a bit line contact junction formed beneath the trench; a plurality of storage node contact junctions formed outside the trench; and a plurality of gate structures each being formed on the substrate disposed between the bit line contact junction and one of the storage node contact junctions. Each sidewall of the trench becomes a part of the individual channels and thus, channel lengths of the transistors in the cell region become elongated. Accordingly, the storage node contact junctions have a decreased level of leakage currents, thereby increasing data retention time.

Claims

1. A memory device, comprising:

a substrate provided with a trench;

a bit line contact junction formed beneath the trench;

a plurality of storage node contact junctions formed outside the trench; and

a plurality of gate structures each being formed on the substrate disposed between the bit line contact junction and one of the storage node contact junctions.

2. The memory device of claim 1, wherein the trench has sidewalls each being a part of a channel.

3. The memory device of claim 1, wherein sidewalls of the trench are sloped by being narrowed down going towards a bottom portion of the trench.

4. The memory device of claim 1, wherein sidewalls of the trench are formed to be perpendicular to a surface of the indented portion of the substrate.

5. The memory device of claim 1, wherein the gate structures, the bit line contact junction and the storage node contact junctions are disposed such that portions of the substrate where the individual sidewalls of the trench are positioned are allocated in the center of respective channel regions.

6. The memory device of claim 1, wherein each of the gate structures includes a first insulation layer, a polysilicon layer, a metal layer and a second insulation layer for use in a hard mask.

7. The memory device of claim 1, wherein each of the gate structures includes a first insulation layer, a planarized polysilicon layer, a metal layer and a second insulation layer for use in a hard mask.

8. The memory device of claim 6, wherein the first insulation layer and the second insulation layer are formed by using silicon oxide and silicon nitride, respectively.

9. The memory device of claim 7, wherein the first insulation layer and the second insulation layer are formed by using silicon oxide and silicon nitride, respectively.

10. A memory device, comprising:

a substrate provided with a trench;

a first contact junction formed beneath the trench;

a plurality of second contact junctions formed outside the trench;

a plurality of gate structures each being formed on the substrate disposed between the first contact junction and one of the second contact junctions;

a first contact plug formed on the first contact junction by filling a space created between the gate structures; and

a plurality of second contact plugs formed on the second contact junctions by filling a space created between the gate structures.

11. The memory device of claim 10, further including:

a bit line connected with the first contact junction through the first contact plug; and

a plurality of storage nodes connected with the second junctions through the second contact plugs, respectively.

12. The memory device of claim 10, wherein the trench has sidewalls each being a part of a channel.

13. The memory device of claim 10, wherein sidewalls of the trench are sloped by being narrowed down going towards a bottom portion of the trench.

14. The memory device of claim 10, wherein sidewalls of the trench are formed to be perpendicular to a surface of the indented portion of the substrate.

15. The memory device of claim 10, wherein the gate structures, the first contact junction and the second contact junctions are disposed such that portions of the substrate where the individual sidewalls of the trench are positioned are allocated in the center of respective channel regions.

16. The memory device of claim 10, wherein each of the gate structures includes a first insulation layer, a polysilicon layer, a metal layer and a second insulation layer for use in a hard mask.

17. The memory device of claim 10, wherein each of the gate structures includes a first insulation layer, a planarized polysilicon layer, a metal layer and a second insulation layer for use in a hard mask.

18. The memory device of claim 16, wherein the first insulation layer and the second insulation layer are formed by using silicon oxide and silicon nitride, respectively.

19. The memory device of claim 17, wherein the first insulation layer and the second insulation layer are formed by using silicon oxide and silicon nitride, respectively.

20. The memory device of claim 10, further including a plurality of spacers formed on each sidewall of the gate structures.

21. A method for fabricating a memory device, comprising the steps of:

etching a portion of a substrate to form a trench;

forming a plurality of gate structures such that one portion of each of the gate structures is disposed within the trench;

performing an ion-implantation process with use of the gate structures as a mask to thereby form a first contact junction beneath the trench and form a plurality of second contact junctions outside the trench; and

forming a first contact plug on the first contact junction and a plurality of second contact plug on the respective contact junctions.

22. The method of claim 21, wherein the step of forming the plurality of gate structures includes the steps of:

sequentially forming a first insulation layer, a polysilicon layer, a metal layer and a second insulation layer on the substrate; and

patterning the first insulation layer, the polysiliocn layer, the metal layer and the second insulation layer by performing a mask process and an etching process.

23. The method of claim 21, wherein the step of forming the plurality of gate structures includes the steps of:

forming a first insulation layer on the substrate;

forming a polysilicon layer on the first insulation layer;

performing a planarization process to obtain a planarized polysilicon layer;

forming a metal layer on the planarized polysilicon layer;

forming a second insulation layer on the metal layer; and

patterning the first insulation layer, the planarized polysiliocn layer, the metal layer and the second insulation layer using a gate mask process and an etching process.

24. The method of claim 21, wherein the step of forming the first contact plug and the second contact plugs includes the steps of:

forming a conductive layer for use in a contact plug over the gate structures; and

performing a chemical mechanical polishing (CMP) process to the conductive layer until the second insulation layer is exposed, thereby obtaining the first contact plug and the plurality of second contact plugs.

25. The method of claim 21, further including the step of applying a re-oxidation process to the gate structures before performing the ion-implantation process.

26. The method of claim 21, wherein the first contact junction and the second contact junctions are formed as a bit line contact junction and storage node contact junctions, respectively.

27. The method of claim 21, after the step of forming the first contact plug and the plurality of second contact plugs, further including the steps of:

forming a bit line connected with the first contact junction through the first contact plug; and

forming a plurality of storage nodes connected with the second contact junction through the second contact plugs, respectively.