Predictive, adaptive power supply for an integrated circuit under test

• US 20060022699A1
• Filed: 09/27/2005
• Published: 02/02/2006
• Est. Priority Date: 01/18/2000
• Status: Active Grant

• Current Assignee: FormFactor Incorporated
• Original Assignee: FormFactor Incorporated
• Inventors: Miller, Charles A., Eldridge, Benjamin N.
• Granted Patent: US 7,245,120 B2
• Time in Patent Office: Days
• US Class Current: 324/754.70
• CPC Class Codes: G01R 31/2851 Testing of integrated circuits [IC] G01R31/317 takes precedence; testing individual devices G01R31/26; testing printed circuits G01R31/2801
• CPC Class Codes: G01R 31/31721 Power aspects, e.g. power supplies for test circuits, power saving during test for scan test G01R31/318575
• CPC Class Codes: G01R 31/31905 Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture
• CPC Class Codes: G01R 31/31924 Voltage or current aspects, e.g. driver, receiver
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C

Abstract

A main power source supplies current through path impedance to a power terminal of an integrated circuit device under test (DUT). The DUT'"'"'s demand for current at the power input terminal temporarily increases following edges of a clock signal applied to the DUT during a test as transistors within the IC switch in response to the clock signal edges. To limit variation (noise) in voltage at the power input terminal, an auxiliary power supply supplies an additional current pulse to the power input terminal to meet the increased demand during each cycle of the clock signal. The magnitude of the current pulse is a function of a predicted increase in current demand during that clock cycle, and of the magnitude of an adaption signal controlled by a feedback circuit provided to limit variation in voltage developed at the DUT'"'"'s power input terminal.

Claims

1-24. -24. (canceled)

25. A method of testing a semiconductor device using a test apparatus, comprising:

creating a characteristic demand record correlated in time with a test sequence for the semiconductor device; and

testing the semiconductor device in accordance with the characteristic demand record.

26. The method of claim 25, wherein the testing comprises:

generating first signals at a first signal source which arrive at the semiconductor device after a delay; and

generating second signals at a second signal source in accordance with the characteristic demand record and a timing offset such that the second signals arrive substantially concurrently with the first signals

27. The method of claim 25, wherein the testing comprises using the characteristic demand record to adjust the behavior of the test apparatus.

28. The method of claim 25, wherein the testing comprises determining a timing offset in accordance with electrical characteristics of a particular test configuration.

29. The method of claim 28, wherein electrical characteristics define a timing delay for a signal from the source to the semiconductor device.

30. The method of claim 25, wherein creating the characteristic demand record comprises applying signals to the semiconductor device and measuring the characteristic demand with respect to time.

31. The method of claim 25, wherein creating the characteristic demand record comprises simulating the characteristic demand with respect to time.

32. The method of claim 25, wherein the testing includes generating signals correlated in time to an applied test vector.

33. The method of claim 25, wherein the characteristic is voltage.

34. The method of claim 25, wherein the characteristic is power.

35. The method of claim 25, wherein the characteristic is current.

36. The method of claim 25, wherein the testing includes using a probe card.

37. A testing apparatus for a semiconductor device, comprising:

a demand recorder for recording a demand record for a characteristic correlated in time with a test sequence for the semiconductor device; and

a probe card for testing the semiconductor device in accordance with the characteristic demand record.

38. The testing apparatus of claim 37, further comprising:

a characteristic generator for generating first signals which arrive at the semiconductor device after a delay; and

a signal source means for generating second signals in accordance with the demand record and a timing offset such that the second signals arrive substantially concurrently with the first signals at the semiconductor device.

39. The testing apparatus of claim 37, wherein the probe card comprises:

means for regulating the characteristic at a semiconductor device using a main source and a secondary source for the characteristic.