Method and apparatus for fail-safe resynchronization with minimum latency
First Claim
1. A synchronization circuit for synchronizing data between receive and transmit mesochronous clocks, comprising:
- a receive clock domain circuit for providing the data clocked by the receive clock;
a first latching circuit, coupled to an output of the receive clock domain circuit, for latching the data on a first edge of the transmit clock;
wherein the receive clock and transmit clock are mesochronous;
a second latching circuit, in parallel with the first latching circuit, for latching the data on a second edge of the transmit clock;
a multiplexing circuit, having inputs coupled to outputs of the first and second latching circuits; and
a phase measurement circuit, configured to measure a phase difference between the receive and transmit clocks and to provide a select signal to the multiplexer in accordance with the phase difference.
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Abstract
A method and circuit for achieving minimum latency data transfer between two mesochronous (same frequency, different phase) clock domains is disclosed. This circuit supports arbitrary phase relationships between two clock domains and is tolerant of temperature and voltage shifts after initialization while maintaining the same output data latency. In one embodiment, this circuit is used on a bus-system to re-time data from receive-domain, clocks to transmit-domain clocks. In such a system the phase relationships between these two clocks is set by the device bus location and thus is not precisely known. By supporting arbitrary phase resynchronization, this disclosure allows for theoretically infinite bus-length and thus no limitation on device count, as well as arbitrary placement of devices along the bus. This ultimately allows support of multiple latency-domains for very long buses.
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2 Claims
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1. A synchronization circuit for synchronizing data between receive and transmit mesochronous clocks, comprising:
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a receive clock domain circuit for providing the data clocked by the receive clock;
a first latching circuit, coupled to an output of the receive clock domain circuit, for latching the data on a first edge of the transmit clock;
wherein the receive clock and transmit clock are mesochronous;
a second latching circuit, in parallel with the first latching circuit, for latching the data on a second edge of the transmit clock;
a multiplexing circuit, having inputs coupled to outputs of the first and second latching circuits; and
a phase measurement circuit, configured to measure a phase difference between the receive and transmit clocks and to provide a select signal to the multiplexer in accordance with the phase difference. - View Dependent Claims (2)
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Specification