Voltage droop suppressing circuit

• US 20060022733A1
• Filed: 08/03/2005
• Published: 02/02/2006
• Est. Priority Date: 06/24/2004
• Status: Active Grant

• Current Assignee: Rajendran Nair
• Original Assignee: Rajendran Nair
• Inventors: Nair, Rajendran
• Granted Patent: US 7,378,898 B2
• Time in Patent Office: Days
• US Class Current: 327/210
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/5384 Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15312 being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/1532 the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/16152 Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/19106 in a mirrored arrangement on two different side of a common die mounting substrate
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

The invention proposes noise suppression circuits that are assembled together with capacitors on a CPU package. Charge is conveyed from the capacitors dedicated to the active noise suppression function through electrical circuit pathways such as controlled electronic switches integrated into a semiconductor substrate. These circuit pathways connect to the capacitor terminals through the package of the active noise suppression semiconductor chip. The circuits within the active device may be any combination of semiconductor switches and/or voltage regulators, and may also contain voltage and current sensing circuitry. The charge transfer switches are designed with control circuitry that dynamically modulate the turn-on threshold voltage of the switches and maintain the switches at an operating point very close to actual turn-on. These enhancements ensure very fast turn-on action for the switches improving voltage droop suppression capability.

Claims

1. An electronic switch circuit, comprising:

A transistor switch device;

A first threshold-modulating sub-circuit, supplying a body bias determined by the desired operational state of the switch to the body node of the transistor switch device;

A second drive sub-circuit, supplying a drive input signal determined by the desired operational state of the switch to the control gate node of the transistor switch device;

A first input signal, of a binary nature, that simultaneously changes the outputs of the first and second sub-circuits, such that the threshold modulating bias difference between the source node and the body node of the transistor switch changes polarity, and the gate drive potential changes so as to change the conduction condition of the transistor switch;

And a common, monolithic semiconductor substrate integrating the switch device and it'"'"'s associated bias, drive and control sub-circuits.

2. The apparatus of claim 1, where the transistor switch device, the first threshold modulating sub-circuit, the second drive sub-circuit, the control and timing circuits are comprised of complementary metal-oxide semiconductor (CMOS) devices.

3. The apparatus of claim 1 formed by CMOS devices fabricated on a wafer substrate doped with electron-donor (n-type) dopant material, such that n-type MOSFET (NMOSFET) devices are formed in p-type doped well (p-well) structures.

4. The apparatus of claim 1, where the transistor switch is an NMOSFET device fabricated within p-well structures in an n-type substrate.

5. The apparatus of claim 1 formed by CMOS devices fabricated on a wafer substrate doped with electron-recipient (p-type) dopant material, such that p-type MOSFET (PMOSFET) devices are formed in n-type doped well (n-well) structures.

6. The apparatus of claim 1, where the transistor switch is a PMOSFET device fabricated within n-well structures in a p-type substrate.

7. The apparatus of claim 1, fabricated upon an n-type substrate, with an n-type transistor switch, where the drain of the n-type transistor switch, the positive or higher power supply inputs to the first and second sub-circuits, and the n-type chip substrate are all connected to the higher voltage input to the integrated circuit chip, and the negative or lower power supply inputs to the first and second sub-circuits are connected to ground.

8. The apparatus of claim 1, fabricated upon a p-type substrate, with an p-type transistor switch, where the source of the p-type transistor switch, the positive or higher power supply inputs to the first and second sub-circuits are all connected to the higher voltage input to the integrated circuit chip, the negative or lower power supply input to the first threshold-modulating sub-circuit and the drain of the p-type power transistor switch is connected to the output or load power supply voltage, and the p-type chip substrate as well as the negative or lower power supply input to the second sub-circuit are connected to ground.

9. The apparatus of claim 1, with capacitance integrated on-chip and connecting between the drain of the transistor switch and ground, and the drive sub-circuit designed so as to provide, for the normally non-conducting state of the transistor switch, a bias voltage input to the transistor switch that allows the flow of a small current through the transistor switch, rendering it at the very beginning of it'"'"'s fully conducting state.

13. Electronic systems comprised of various integrated and discrete electronic circuits and devices, electrochemical, electro-thermal, electro-mechanical and electro-optic devices that employ the apparatus of claim 1 in any embodiment.

10. A method for the fast switching of a transistor device, comprising:

The application of a ‘

reverse body bias’

between the body terminal and the source terminal of the device thereby increasing its turn-on threshold voltage;

The provision of a gate bias voltage that renders the transistor switch at the very beginning of its transition to a fully conducting state;

And the simultaneous transitions, of the gate bias voltage to the full value of the drive signal necessary to render the transistor switch to it'"'"'s fully conducting state, and of the substrate bias signal such as to provide a ‘

forward body bias’

voltage between the body terminal and the source terminal of the transistor switch device.

11. The method of claim 10, applied to an NMOSFET transistor switch connected at its drain terminal to a higher power supply voltage and at its source terminal to a lower power supply voltage, where the reverse body bias is generated automatically by the voltage at the source node of the transistor switch with respect to the ground potential at the output of a bias sub-circuit connecting to the body terminal, and where the forward body bias is generated by the transition of the output of the bias sub-circuit to the voltage at the drain terminal of the transistor switch device.

12. The method of claim 10, applied to an NMOSFET transistor switch, where an alternate path for current flow is provided, for a period after the transistor switch is transitioned to its non-conducting state, through the body terminal biasing sub-circuit, which may be a simple CMOS inverter, and the forward-biased source junction of the transistor switch.

14. Electronic systems comprised of various integrated and discrete electronic circuits and devices, electro-chemical, electro-thermal, electro-mechanical and electro-optic devices that employ the method of claim 10 in any embodiment.