276-Pin buffered memory module with enhanced fault tolerance

• US 20060023482A1
• Filed: 07/30/2004
• Published: 02/02/2006
• Est. Priority Date: 07/30/2004
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Dreps, Daniel M., Kellogg, Mark W., Rippens, Roger A., Ferriaolo, Frank D., Gower, Kevin C.
• Granted Patent: US 7,224,595 B2
• Time in Patent Office: Days
• US Class Current: 365/63
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports

Abstract

A dual inline memory module (DIMM) includes a card having a length of about 151.2 to about 151.5 millimeters, a plurality of individual local memory devices attached to the card, and a buffer device attached to the card, the buffer device configured for converting a packetized memory interface. The card includes at least 276 pins configured thereon.

Claims

1. A dual inline memory module (DIMM), comprising:

a card having a length of about 151.2 to about 151.5 millimeters;

a plurality of individual local memory devices attached to said card;

a buffer device attached to said card, said buffer device configured for converting a packetized memory interface; and

said card including at least 276 pins configured thereon.

2. The DIMM of claim 1, further comprising a positioning key formed on said card, wherein said positioning key is located at a non-center position with respect to a length of the card.

3. The DIMM of claim 1, wherein said at least 276 pins are arranged in a first row of pins and a second row of pins behind said first row.

4. The DIMM of claim 3, further comprising a plurality of redundant pins among said at least 276 pins, wherein a given redundant pin with respect to a given primary function pin is located directly behind said primary function pin.

5. The DIMM of claim 1, wherein said at least 276 pins further comprise a pair of continuity pins, one of said pair of continuity pins located at one end of said card, and the other of said pair of continuity pins located at the opposite end of said card.

6. A dual inline memory module (DIMM), comprising:

a card having a length of about 151.35 millimeters;

a plurality of individual local memory devices attached to the card;

a buffer device attached to the card, said buffer device configured to re-drive information to one or more external memory modules in a cascading manner; and

at least one positioning key formed on the card.

7. The DIMM of claim 6, further comprising a plurality of at least 276 pins formed on said card.

8. The DIMM of claim 7, wherein at least one positioning key is located at a non-center position with respect to a length of the card.

9. The DIMM of claim 7, wherein said at least 276 pins are arranged in a first row of pins and a second row of pins behind said first row.

10. The DIMM of claim 9, further comprising a plurality of redundant pins among said at least 276 pins, wherein a given redundant pin with respect to a given primary function pin is located directly behind said primary function pin.

11. The DIMM of claim 7, wherein said at least 276 pins further comprise a pair of continuity pins, one of said pair of continuity pins located at one end of said card, and the other of said pair of continuity pins located at the opposite end of said card.

12. A computer memory system, comprising:

a memory controller device; and

a first dual inline memory module (DIMM) coupled to said memory controller device through a set of at least two single-ended busses, said first DIMM comprising a card having a length of about 151.2 to about 151.5 millimeters, a plurality of individual local memory devices attached to said card, and a buffer device attached to said card, said buffer device configured for converting a packetized memory interface.

13. The computer memory system of claim 12 further comprising error code correction (ECC) logic for identifying and correcting bus faults.

14. The computer memory system of claim 12 further comprising a set of at least two high-speed busses for connecting said first DIMM to at least one of:

said memory controller device and a second DIMM.

15. The computer memory system of claim 12, wherein said first DIMM further comprises a plurality of at least 276 pins formed on said card.

16. The computer memory system of claim 15, wherein at least one positioning key is located at a non-center position with respect to said length of the card.

17. The computer memory system of claim 15, wherein said at least 276 pins are arranged in a first row of pins and a second row of pins behind said first row.

18. The computer memory system of claim 17, further comprising a plurality of redundant pins among said at least 276 pins, wherein a given redundant pin with respect to a given primary function pin is located directly behind said primary function pin.

19. The computer memory system of claim 15, wherein said at least 276 pins further comprise a pair of continuity pins, one of said pair of continuity pins located at one end of said card, and the other of said pair of continuity pins located at the opposite end of said card.

20. A computer memory system, comprising:

a dual inline memory module (DIMM) comprising a card, a plurality of individual local memory devices attached to said card, and a buffer device attached to said card, said buffer device configured for converting a packetized memory interface;

a plurality of high-speed busses in communication with said DIMM for implementing a cascade connection to upstream and downstream devices with respect to said DIMM; and

said DIMM further having a plurality of high-speed bus interface pins arranged on said card, such that;

for a first high-speed bus, a first portion of said high-speed bus interface pins associated therewith is located on one side of said card, with respect to a midpoint of a length of said card, and a second portion of said high-speed bus interface pins associated therewith located on the opposite side of said card, with respect to said midpoint; and

for a second high-speed bus, the high-speed bus interface pins are clustered around the center of said card, with respect to said midpoint.

21. The computer memory system of claim 20, wherein said DIMM further comprises a plurality of at least 276 pins formed on said card.

22. The computer memory system of claim 20, wherein at least one positioning key is located at a non-center position with respect to said length of the card.

23. The computer memory system of claim 20, wherein said at least 276 pins are arranged in a first row of pins and a second row of pins behind said first row.

24. The computer memory system of claim 20, wherein the length is about 151.2 to about 151.5 millimeters.

25. The computer memory system of claim 20, further comprising a plurality of redundant pins among said at least 276 pins, wherein a given redundant pin with respect to a given primary function pin is located directly behind said primary function pin.

26. A dual inline memory module (DIMM), comprising:

a card having a length of about 151.2 to about 151.5 millimeters;

a plurality of individual local memory devices attached to said card;

a buffer device attached to said card, said buffer device configured for converting a packetized memory interface; and

said card including at least 276 pins configured thereon, wherein a first portion of said pins is configured to operate at a first supply voltage, and a second portion of said pins is configured to operate at a second supply voltage.

27. The DIMM of claim 26, wherein, said first supply voltage is used to operate logic devices associated with said buffer device, and said second supply voltage is used to operate said plurality of individual local memory devices.

28. The DIMM of claim 27, further comprising a positioning key formed on said card, wherein said positioning key is located at a non-center position with respect to a length of the card.

29. The DIMM of claim 27, wherein said at least 276 pins are arranged in a first row of pins and a second row of pins behind said first row.

30. The DIMM of claim 29, further comprising a plurality of redundant pins among said at least 276 pins, wherein a given redundant pin with respect to a given primary function pin is located directly behind said primary function pin.

31. The DIMM of claim 30, wherein said at least 276 pins further comprise a pair of continuity pins, one of said pair of continuity pins located at one end of said card, and the other of said pair of continuity pins located at the opposite end of said card.