Novel NVRAM memory cell architecture that integrates conventional SRAM and flash cells

• US 20060023503A1
• Filed: 02/11/2005
• Published: 02/02/2006
• Est. Priority Date: 07/28/2004
• Status: Active Grant

• Current Assignee: Abedneja Assets AG LLC (Intellectual Ventures LLC)
• Original Assignee: Aplus Flash Technology, Inc.
• Inventors: Lee, Peter
• Granted Patent: US 7,164,608 B2
• Time in Patent Office: Days
• US Class Current: 365/185.50
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
• CPC Class Codes: G11C 14/0063 and the nonvolatile element is an EEPROM element, e.g. a floating gate or MNOS transistor
• CPC Class Codes: G11C 16/10 Programming or data input circuits

Abstract

A nonvolatile SRAM array has an array of integrated nonvolatile SRAM circuits arranged in rows and columns on a substrate. Each of the integrated nonvolatile SRAM circuits includes an SRAM cell, a first and second nonvolatile memory element. The SRAM cell has a latched memory element in communication first and second nonvolatile memory elements to receive and permanently retain the digital signal from the latched memory element. A power detection circuit detects a power interruption and a power initiation and communicates the detection of the power interruption and power initiation to the plurality of integrated nonvolatile SRAM circuits. The SRAM cell, upon detection of the power interruption, transmits the digital signal to the first and second nonvolatile memory elements. The SRAM cell of each of the nonvolatile static random access memories upon detection of the power initiation, receives the digital signal from the first and second nonvolatile memory elements.

Claims

1. An integrated nonvolatile static random access memory circuit formed on a substrate, said integrated nonvolatile static random access memory circuit comprising:

a static random access memory cell comprising;

a latched memory element to retain a digital signal indicative of a data bit, and

a first access transistor and a second access transistor connected to allow control access of a first bit line and a second bit line to said latched memory element for writing and reading said digital signal to and from said latched memory element,

said first and second access transistors having control gates in communication with a word line for controlling access of said latched memory element to said first and second bit lines;

a first nonvolatile memory element in communication with said latched memory element through a first terminal to receive and permanently retain said digital signal from said latched memory element; and

a second nonvolatile memory element in communication with said latched memory element through a first terminal to receive and permanently retain a complementary level of said digital signal from said latched memory element.

2. The integrated nonvolatile static random access memory circuit of claim 1 wherein said first terminal of said first nonvolatile memory element is connected to a storage node between the first access transistor and the latched memory element to transfer said digital signal to said first nonvolatile memory element.

3. The integrated nonvolatile static random access memory circuit of claim 1 wherein said first terminal of said second nonvolatile memory element is connected to a complementary storage node between the second access transistor and the latched memory element to transfer said digital signal to said first nonvolatile memory element.

4. The integrated nonvolatile static random access memory circuit of claim 1 wherein said first and second nonvolatile memory elements are comprised of:

a first select gating transistor including a drain connected to the first terminal and a gate connected to receive a first select gating signal;

a floating gate transistor having a drain connected to a source of said first gating transistor such that when said first select gating signal is activated said drain of said floating gate is connected to said latched memory element and a gate connected to receive a read, program, and erase signals for said floating gate transistor; and

a second select gating transistor including a drain connected to a source of said floating gate transistor, a source connected to receive a source line signal for reading, programming, and erasing said floating gate transistor, and a gate to receive a second select gating signal for connecting said source line signal to said source of said floating gate transistor.

5. The integrated nonvolatile static random access memory circuit of claim 4 wherein said static random access memory cell retains said digital signal as volatile digital data by setting the first gating signal such that the first select gating transistors of the first and second nonvolatile memory elements are deactivated and said static random access memory cell is effectively not in communication with said first and second nonvolatile memory elements.

6. The integrated nonvolatile static random access memory circuit of claim 4 wherein said first and second nonvolatile memory elements are erased by the steps of:

setting said first gating select signal to deactivate said first select gating transistors of said first and second nonvolatile memory elements;

applying said erase signal to said gate of said floating gate transistors of said first and second nonvolatile memory elements;

applying said second gating select signal to activate said select gating transistor of said first and second nonvolatile memory elements to connect said sources of said floating gate transistors of said first and second nonvolatile memory elements to said source line; and

applying a ground reference voltage to said source line.

7. The integrated nonvolatile static random access memory circuit of claim 6 wherein the erase signal from approximately −

15V to approximately −

22V.

8. The integrated nonvolatile static random access memory circuit of claim 4 wherein said digital signal is programmed to said first nonvolatile memory element and the complementary of said digital signal are programmed to said second nonvolatile memory element by the steps of:

setting said first gating select signal to activate said first select gating transistors of said first and second nonvolatile memory elements;

applying said program signal to said gate of said floating gate transistors of said first and second nonvolatile memory elements;

applying said second gating select signal to activate said select gating transistors of said first and second nonvolatile memory elements to connect said sources of said floating gate transistors of said first and second nonvolatile memory elements to said source line; and

applying a ground reference voltage to said source line.

9. The integrated nonvolatile static random access memory circuit of claim 8 wherein the program signal is from approximately +15V to approximately +22V.

10. A nonvolatile static random access memory array comprising:

a plurality of integrated nonvolatile static random access memory circuits arrange in an array of rows and columns and formed on a substrate, said integrated nonvolatile static random access memory circuit comprising;

a static random access memory cell comprising;

a latched memory element to retain a digital signal indicative of a data bit, and

a first access transistor and a second access transistor connected to allow control access of a first bit line and a second bit line to said latched memory element for writing and reading said digital signal to and from said latched memory element,

said first and second access transistors having control gates in communication with a word line for controlling access of said latched memory element to said first and second bit lines;

a first nonvolatile memory element in communication with said latched memory element through a first terminal to receive and permanently retain said digital signal from said latched memory element; and

a second nonvolatile memory element in communication with said latched memory element through a first terminal to receive and permanently retain a complementary level of said digital signal from said latched memory element.

11. The nonvolatile static random access memory array of claim 10 further comprising a power detection circuit in communication with the plurality of integrated nonvolatile static random access memory circuits to detect a power interruption and a power initiation and communicate said detection of said power interruption and detection of said power initiation to said plurality of integrated nonvolatile static random access memory circuits.

12. The nonvolatile static random access memory array of claim 11 wherein, said static random access memory cell of each of the nonvolatile static random access memories upon detection of said power interruption, transmits said digital signal and a complementary of said digital signal to said first and second nonvolatile memory elements.

13. The nonvolatile static random access memory array of claim 11 wherein, said static random access memory cell of each of the nonvolatile static random access memories upon detection of said power initiation, receives said digital signal and a complementary of said digital signal from said first and second nonvolatile memory elements.

14. The nonvolatile static random access memory array of claim 10 wherein said first terminal of said first nonvolatile memory element of each of the plurality of integrated nonvolatile static random access memory circuits is connected to a storage node between the first access transistor and the latched memory element to transfer said digital signal to said first nonvolatile memory element.

15. The nonvolatile static random access memory array of claim 10 wherein said first terminal of said second nonvolatile memory element of each of the plurality of integrated nonvolatile static random access memory circuits is connected to a complementary storage node between the second access transistor and the latched memory element to transfer said digital signal to said first nonvolatile memory element.

16. The nonvolatile static random access memory array of claim 10 wherein said first and second nonvolatile memory elements of each of the plurality of integrated nonvolatile static random access memory circuits are comprised of:

a first select gating transistor including a drain connected to the first terminal and a gate connected to receive a first select gating signal;

a floating gate transistor having a drain connected to a source of said first gating transistor such that when said first select gating signal is activated said drain of said floating gate is connected to said latched memory element and a gate connected to receive a read, program, and erase signals for said floating gate transistor; and

a second select gating transistor including a drain connected to a source of said floating gate transistor, a source connected to receive a source line signal for reading, programming, and erasing said floating gate transistor, and a gate to receive a second select gating signal for connecting said source line signal to said source of said floating gate transistor.

17. The nonvolatile static random access memory array of claim 13 wherein said static random access memory cell of each of the plurality of integrated nonvolatile static random access memory circuits retains said digital signal as volatile digital data by setting the first gating signal such that the first select gating transistors of the first and second nonvolatile memory elements are deactivated and said static random access memory cell is effectively not in communication with said first and second nonvolatile memory elements.

18. The nonvolatile static random access memory array of claim 16 wherein said first and second nonvolatile memory elements of each of the plurality of integrated nonvolatile static random access memory circuits are erased by the steps of:

setting said first gating select signal to deactivate said first select gating transistors of said first and second nonvolatile memory elements;

applying said erase signal to said gate of said floating gate transistors of said first and second nonvolatile memory elements;

applying said second gating select signal to activate said select gating transistor of said first and second nonvolatile memory elements to connect said sources of said floating gate transistors of said first and second nonvolatile memory elements to said source line; and

applying a ground reference voltage to said source line.

19. The nonvolatile static random access memory array of claim 18 wherein the erase signal from approximately −

15V to approximately −

22V.

20. The nonvolatile static random access memory array of claim 16 wherein said digital signal is programmed to said first nonvolatile memory element of each of the plurality of integrated nonvolatile static random access memory circuits and the complementary of said digital signal are programmed to said second nonvolatile memory element of each of the plurality of integrated nonvolatile static random access memory circuits by the steps of:

setting said first gating select signal to activate said first select gating transistors of said first and second nonvolatile memory elements;

applying said program signal to said gate of said floating gate transistors of said first and second nonvolatile memory elements;

applying said second gating select signal to activate said select gating transistors of said first and second nonvolatile memory elements to connect said sources of said floating gate transistors of said first and second nonvolatile memory elements to said source line; and

applying a ground reference voltage to said source line.

21. The nonvolatile static random access memory array of claim 20 wherein the program signal is from approximately +15V to approximately +22V.

22. A method for forming an integrated nonvolatile static random access memory circuit on a substrate comprising the steps of:

forming a static random access memory cell by the steps of;

forming a latched memory element on said substrate to retain a digital signal indicative of a data bit,

forming a first access transistor and a second access transistor on said substrate,

connecting said first and second access transistors to allow control access of a first bit line and a second bit line to said latched memory element for writing and reading said digital signal to and from said latched memory element, and

connecting control gates of said first and second access transistors having control gates to be in communication with a word line for controlling access of said latched memory element to said first and second bit lines;

forming a first nonvolatile memory element on said substrate;

placing said first nonvolatile memory element in communication with said latched memory element through a first terminal to receive and permanently retain said digital signal from said latched memory element;

forming a second nonvolatile memory element; and

placing said second nonvolatile memory element in communication with said latched memory element through a first terminal to receive and permanently retain a complementary level of said digital signal from said latched memory element.

23. The method for forming the integrated nonvolatile static random access memory circuit of claim 22 further comprising the step of connecting said first terminal of said first nonvolatile memory element to a storage node between the first access transistor and the latched memory element to transfer said digital signal to said first nonvolatile memory element.

24. The method for forming the integrated nonvolatile static random access memory circuit of claim 22 further comprising the step of connecting said first terminal of said second nonvolatile memory element to a complementary storage node between the second access transistor and the latched memory element to transfer said digital signal to said first nonvolatile memory element.

25. The method for forming the integrated nonvolatile static random access memory circuit of claim 22 wherein forming said first and second nonvolatile memory elements on said substrate comprise the steps of:

forming a first select gating transistor including a drain connected to the first terminal and a gate connected to receive a first select gating signal,

forming a floating gate transistor having a drain connected to a source of said first gating transistor such that when said first select gating signal is activated said drain of said floating gate is connected to said latched memory element and a gate connected to receive a read, program, and erase signals for said floating gate transistor; and

forming a second select gating transistor including a drain connected to a source of said floating gate transistor, a source connected to receive a source line signal for reading, programming, and erasing said floating gate transistor, and a gate to receive a second select gating signal for connecting said source line signal to said source of said floating gate transistor.

26. The method for forming the integrated nonvolatile static random access memory circuit of claim 25 wherein said static random access memory cell retains said digital signal as volatile digital data by setting the first gating signal such that the first select gating transistors of the first and second nonvolatile memory elements are deactivated and said static random access memory cell is effectively not in communication with said first and second nonvolatile memory elements.

27. The method for forming the integrated nonvolatile static random access memory circuit of claim 25 wherein said first and second nonvolatile memory elements are erased by the steps of:

transistors of said first and second nonvolatile memory elements;

applying said erase signal to said gate of said floating gate transistors of said first and second nonvolatile memory elements;

applying said second gating select signal to activate said select gating transistor of said first and second nonvolatile memory elements to connect said sources of said floating gate transistors of said first and

second nonvolatile memory elements to said source line; and

applying a ground reference voltage to said source line.

28. The method for forming the integrated nonvolatile static random access memory circuit of claim 27 wherein the erase signal from approximately −

15V to approximately −

22V.

29. The method for forming the integrated nonvolatile static random access memory circuit of claim 25 wherein said digital signal is programmed to said first nonvolatile memory element and the complementary of said digital signal are programmed to said second nonvolatile memory element by the steps of:

setting said first gating select signal to activate said first select gating transistors of said first and second nonvolatile memory elements;

applying said program signal to said gate of said floating gate transistors of said first and second nonvolatile memory elements;

applying said second gating select signal to activate said select gating transistors of said first and second nonvolatile memory elements to connect said sources of said floating gate transistors of said first and second nonvolatile memory elements to said source line; and

applying a ground reference voltage to said source line.

30. The method for forming the integrated nonvolatile static random access memory circuit of claim 29 wherein the program signal is from approximately +15V to approximately +22V.