Semiconductor integrated circuit device
First Claim
1. A semiconductor integrated circuit device comprising:
- a plurality of memory cells each comprised of a storage in which input and output terminals of two inverter circuits are cross-connected and a selection MOSFET provided between said storage and complementary bit lines and whose gate is connected to a word line;
an address selection circuit for setting all of word lines to a non-selection level in a standby state where any of writing and reading operations is not performed on said memory cell; and
a substrate bias switching circuit, wherein in normal operation, said substrate bias switching circuit supplies a power source voltage to an N-type well in which a P-channel MOSFET of a memory cell is formed and supplies a ground potential of the circuit to a P-type well in which an N-channel MOSFET is formed, and wherein in said standby state, said substrate bias switching circuit supplies to said N-type well a predetermined voltage which is lower than said power source voltage and by which a PN junction between the N-type well and the source of the P-channel MOSFET is not forward biased, and supplies to said P-type well a predetermined voltage which is higher than said ground potential and by which a PN junction between the P-type well and the source of the N-channel MOSFET is not forward biased.
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Accused Products
Abstract
The present invention provides a semiconductor integrated circuit device having an SRAM in which leak current is reduced. In an SRAM comprising a plurality of memory cells each constructed by a storage in which input and output terminals of two inverter circuits are cross-connected and a selection MOSFET provided between the storage and complementary bit lines and whose gate is connected to a word line, a substrate bias switching circuit is provided. In normal operation, the substrate bias switching circuit supplies a power source voltage to an N-type well in which a P-channel MOSFET of a memory cell is formed and supplies a ground potential of the circuit to a P-type well in which an N-channel MOSFET is formed. In the standby state, the substrate bias switching circuit supplies a predetermined voltage which is lower than the power source voltage and by which a PN junction between the N-type well and the source of the P-channel MOSFET is not forward biased to the N-type well, and supplies a predetermined voltage which is higher than the ground potential and by which a PN junction between the P-type well and the source of the N-channel MOSFET is not forward biased to the P-type well.
20 Citations
5 Claims
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1. A semiconductor integrated circuit device comprising:
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a plurality of memory cells each comprised of a storage in which input and output terminals of two inverter circuits are cross-connected and a selection MOSFET provided between said storage and complementary bit lines and whose gate is connected to a word line;
an address selection circuit for setting all of word lines to a non-selection level in a standby state where any of writing and reading operations is not performed on said memory cell; and
a substrate bias switching circuit, wherein in normal operation, said substrate bias switching circuit supplies a power source voltage to an N-type well in which a P-channel MOSFET of a memory cell is formed and supplies a ground potential of the circuit to a P-type well in which an N-channel MOSFET is formed, and wherein in said standby state, said substrate bias switching circuit supplies to said N-type well a predetermined voltage which is lower than said power source voltage and by which a PN junction between the N-type well and the source of the P-channel MOSFET is not forward biased, and supplies to said P-type well a predetermined voltage which is higher than said ground potential and by which a PN junction between the P-type well and the source of the N-channel MOSFET is not forward biased. - View Dependent Claims (2, 3, 4, 5)
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Specification