Memory module and method having improved signal routing topology

• US 20060023528A1
• Filed: 09/28/2005
• Published: 02/02/2006
• Est. Priority Date: 06/11/2003
• Status: Active Grant

• Current Assignee: Round Rock Research LLC
• Original Assignee: George E. Pax, Roy E. Greeff
• Inventors: Greeff, Roy E., Pax, George E.
• Granted Patent: US 7,282,947 B2
• Time in Patent Office: Days
• US Class Current: 365/202
• CPC Class Codes: G11C 11/409 Read-write [R-W] circuits
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: H05K 1/025 Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance H05K1/024 and H05K1/0243 take precedence; for semiconductor devices H01L23/66
• CPC Class Codes: H05K 1/181 associated with surface mounted components
• CPC Class Codes: H05K 2201/09254 Branched layout
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology. The tree includes several branches each of which includes two transmission lines coupled only at its ends to either another transmission line or one of the memory devices. The branches are arranged in several layers of hierarchy, with the transmission lines in branches having the same hierarchy having the same length. Each transmission line preferably has a characteristic impedance that is half the characteristic impedance of any pair of downstream transmission lines to which it is coupled to provide impedance matching. A dedicated transmission line is used to couple an additional memory device, which may or may not be an error checking memory device, to the register.

Claims

1-34. -34. (canceled)

35. A processor-based system, comprising:

a processor having a processor bus;

a system controller coupled to the processor bus, the system controller having a system memory port and a peripheral device port;

at least one input device coupled to the peripheral device port of the system controller;

at least one output device coupled to the peripheral device port of the system controller;

at least one data storage device coupled to the peripheral device port of the system controller; and

a memory module coupled to the system memory port of the system controller, the memory module comprising;

a plurality of memory devices;

an active memory component having a plurality of terminals, the active memory component being coupled to the system memory port of the system controller; and

a respective conductor tree coupling each of the terminals of the active memory component to a terminal of each of the plurality of memory devices, each of the conductor trees comprising at least one branch, each branch including a pair of transmission lines each of which is connected at only its ends to either one of the memory devices, the respective terminal of the active memory component, or to an end of another of the transmission lines, the transmission lines being arranged in a plurality of hierarchies with the transmission lines in the same hierarchy have the same length.

36. The processor-based system of claim 35 wherein the active memory component comprises a register for storing address and command signals and outputting the stored address and command signals to the memory devices.

37. The processor-based system of claim 35 wherein each of the transmission lines in each branch has a characteristic impedance, and wherein the characteristic impedance of each transmission line is approximately half the characteristic impedance of any transmission line to which it is coupled downsteam of the active memory component.

38. The processor-based system of claim 35 wherein the plurality of memory devices comprises a plurality of dynamic random access memory devices.

39. The processor-based system of claim 35, further comprising:

an additional memory device other than the plurality of memory devices; and

a plurality of dedicated transmission lines each coupling a respective one of several of the terminals of the active memory component to respective terminals of the additional memory device.

40. The processor-based system of claim 39 wherein the additional memory device comprises an error checking memory device.

41. The processor-based system of claim 39 wherein the lengths of the dedicated transmission lines from the active memory component to the additional memory device are substantially equal to the lengths of the transmission lines in the tree from the active memory component to each of the plurality of memory devices.

42. The processor-based system of claim 35 wherein the transmission lines in all of the hierarchies have the same length.

43. The processor-based system of claim 35 wherein the memory module comprises 2^N of the memory devices, and wherein the tree comprise N hierarchies of branches.

44. The processor-based system of claim 35 wherein each of the transmission lines have a characteristic impedance, and wherein the transmission lines in the same hierarchy have the same characteristic impedance.

45. The processor-based system of claim 44 wherein each of the transmission lines in the same hierarchy have the same electrical characteristics.

46. The processor-based system of claim 35 wherein the terminals of the active memory component comprises output terminals, and the terminals of the memory devices comprise input terminals.

47. A processor-based system, comprising:

a processor having a processor bus;

a system controller coupled to the processor bus, the system controller having a system memory port and a peripheral device port;

at least one input device coupled to the peripheral device port of the system controller;

at least one output device coupled to the peripheral device port of the system controller;

at least one data storage device coupled to the peripheral device port of the system controller; and

a memory module coupled to the system memory port of the system controller, the memory module comprising;

a plurality of memory devices;

an active memory component having a plurality of terminals, the active memory component being coupled to the system memory port of the system controller; and

a respective conductor tree coupling each of the terminals of the active memory component to a terminal of each of the plurality of memory devices, each of the conductor trees comprising at least one branch, each branch including a pair of transmission lines each of which is connected at only its ends to either one of the memory devices, the respective terminal of the active memory component, or to an end of another of the transmission lines, the transmission lines being arranged in a plurality of hierarchies with the transmission lines in the same hierarchy having electrical and physical characteristics that cause the signal propagation times through the transmission lines in the same hierarchy to be substantially equal to each other.

48. The processor-based system of claim 47 wherein the active memory component comprises a register for storing address and command signals and outputting the stored address and command signals to the memory devices.

49. The processor-based system of claim 47 wherein each of the transmission lines in each branch has a characteristic impedance, and wherein the characteristic impedance of each transmission line is approximately half the characteristic impedance of any transmission line to which it is coupled downsteam of the active memory component.

50. The processor-based system of claim 47 wherein the plurality of memory devices comprises a plurality of dynamic random access memory devices.

51. The processor-based system of claim 47, further comprising:

an additional memory device other than the plurality of memory devices; and

a plurality of dedicated transmission lines each coupling a respective one of several of the terminals of the active memory component to respective terminals of the additional memory device.

52. The processor-based system of claim 51 wherein the additional memory device comprises an error checking memory device.

53. The processor-based system of claim 51 wherein the signal propagation times through the dedicated transmission lines from the active memory component to the additional memory device are substantially equal to the signal propagation times through the transmission lines in the tree from the active memory component to each of the plurality of memory devices.

54. The processor-based system of claim 47 wherein the transmission lines in all of the hierarchies have the same signal propagation times.

55. The processor-based system of claim 47 wherein the memory module comprises 2^N of the memory devices, and wherein the tree comprise N hierarchies of branches.

56. The processor-based system of claim 47 wherein each of the transmission lines have a characteristic impedance, and wherein the transmission lines in the same hierarchy have the same characteristic impedance.

57. The processor-based system of claim 56 wherein each of the transmission lines in the same hierarchy have the same electrical characteristics.

58. The processor-based system of claim 47 wherein the transmission lines in the same hierarchy have the same lengths.

59. The processor-based system of claim 47 wherein the terminals of the active memory component comprises output terminals, and the terminals of the memory devices comprise input terminals.