Memory module and method having improved signal routing topology
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Abstract
A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology. The tree includes several branches each of which includes two transmission lines coupled only at its ends to either another transmission line or one of the memory devices. The branches are arranged in several layers of hierarchy, with the transmission lines in branches having the same hierarchy having the same length. Each transmission line preferably has a characteristic impedance that is half the characteristic impedance of any pair of downstream transmission lines to which it is coupled to provide impedance matching. A dedicated transmission line is used to couple an additional memory device, which may or may not be an error checking memory device, to the register.
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Citations
59 Claims
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1-34. -34. (canceled)
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35. A processor-based system, comprising:
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a processor having a processor bus;
a system controller coupled to the processor bus, the system controller having a system memory port and a peripheral device port;
at least one input device coupled to the peripheral device port of the system controller;
at least one output device coupled to the peripheral device port of the system controller;
at least one data storage device coupled to the peripheral device port of the system controller; and
a memory module coupled to the system memory port of the system controller, the memory module comprising;
a plurality of memory devices;
an active memory component having a plurality of terminals, the active memory component being coupled to the system memory port of the system controller; and
a respective conductor tree coupling each of the terminals of the active memory component to a terminal of each of the plurality of memory devices, each of the conductor trees comprising at least one branch, each branch including a pair of transmission lines each of which is connected at only its ends to either one of the memory devices, the respective terminal of the active memory component, or to an end of another of the transmission lines, the transmission lines being arranged in a plurality of hierarchies with the transmission lines in the same hierarchy have the same length. - View Dependent Claims (36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46)
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47. A processor-based system, comprising:
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a processor having a processor bus;
a system controller coupled to the processor bus, the system controller having a system memory port and a peripheral device port;
at least one input device coupled to the peripheral device port of the system controller;
at least one output device coupled to the peripheral device port of the system controller;
at least one data storage device coupled to the peripheral device port of the system controller; and
a memory module coupled to the system memory port of the system controller, the memory module comprising;
a plurality of memory devices;
an active memory component having a plurality of terminals, the active memory component being coupled to the system memory port of the system controller; and
a respective conductor tree coupling each of the terminals of the active memory component to a terminal of each of the plurality of memory devices, each of the conductor trees comprising at least one branch, each branch including a pair of transmission lines each of which is connected at only its ends to either one of the memory devices, the respective terminal of the active memory component, or to an end of another of the transmission lines, the transmission lines being arranged in a plurality of hierarchies with the transmission lines in the same hierarchy having electrical and physical characteristics that cause the signal propagation times through the transmission lines in the same hierarchy to be substantially equal to each other. - View Dependent Claims (48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59)
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Specification