Selectively strained MOSFETs to improve drive current

• US 20060024879A1
• Filed: 07/31/2004
• Published: 02/02/2006
• Est. Priority Date: 07/31/2004
• Status: Abandoned Application

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chang, Cheng-Hung, Fu, Chu-Yun
• Application Number:
  US10/902,973
• Publication Number:
  US 20060024879A1
• Time in Patent Office: Days
• US Class Current: 438/216
• CPC Class Codes: H01L 21/0214 the material being a silicon oxynitride, e.g. SiON or SiON:H
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/3185 of siliconnitrides
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

A MOSFET device pair with improved drive current and a method for producing the same to selectively introduce strain into a respective N-type and P-type MOSFET device channel region, the method including forming a compressive stressed nitride layer on over the P-type MOSFET device and a tensile stressed nitride layer on the N-type MOSFET device followed by forming a PMD layer having a less compressive or tensile stress.

Claims

1. A method for introducing strain into a MOSFET channel region comprising the steps of:

providing a first and second MOSFET device having a respective first polarity and second polarity opposite from the first polarity selected from the group consisting of P and N type on a semiconducting substrate;

forming a first stressed nitride layer having a first stress type selected from the group consisting of compressive and tensile stress over the first and second MOSFET device active areas;

removing the first stressed nitride layer overlying the second MOSFET device active area;

forming a second stressed nitride layer having a second stress type opposite the first stress type over the first and second MOSFET device active areas;

removing the second stressed nitride layer overlying the first MOSFET device active area; and

,

forming a dielectric insulating layer over the first and second MOSFET device active areas having a less compressive or tensile stress.

2. The method of claim 1, wherein the first and second stressed nitride layers are formed by a mixed frequency PECVD method.

3. The method of claim 2, wherein the mixed frequency PECVD method comprises at least two RF power sources to produce a mixed frequency signal, a first RF power source operating at a frequency of from about 300 KHz to 500 KHz and a second RF power source operating at a frequency of about 13 to 14 MHz.

4. The method of claim 1, wherein the first and second MOSFET devices further comprise metal silicide regions selected from the group consisting of cobalt silicide and nickel silicide.

5. The method of claim 1, wherein the first and second stressed nitride layers are formed at a temperature of less than about 550°

C.

6. The method of claim 1, wherein first and second stressed layers are selected from the group consisting of silicon nitride and silicon oxynitride.

7. The method of claim 1, wherein the dielectric insulating layer is selected from the group consisting of undoped silicate (USG) glass and phosphorous silicate glass (PSG) deposited according to a CVD method selected from the group consisting of atmospheric and sub-atmospheric CVD.

8. The method of claim 1, wherein the dielectric insulating layer is selected from the group consisting of undoped and P-doped spin-on glass (SOG).

9. The method of claim 1, wherein the stressed nitride layers are formed comprising silane containing precursors selected from the group consisting of (SiH₄), disilane (Si₂H₆), trisilane (Si₃H₈), dichlorosilane (SiH₂Cl₂), trichlorosilane (SiHCl₃), and hexacholorodisilane (HCD)(Si₂Cl₆).

10. The method of claim 1, wherein the stressed nitride layers are formed having a stress level absolute value greater than about 7×

10⁹ dynes/cm².

11. The method of claim 1, wherein the semiconductor substrate comprises a material selected from the group consisting of silicon, strained semiconductor, compound semiconductor, multi-layered semiconductors, silicon on strained semiconductor, silicon on insulator, and combinations thereof.

12. The method of claim 1, wherein the semiconductor substrate comprises silicon on insulator (SOI), stacked SOI (SSOI), stacked SiGe on insulator (S—

SiGeOI), SiGeOI, and GeOI, and combinations thereof.

13. The method of claim 1, wherein the stressed nitride layers are formed having a thickness from about 100 Angstroms to about 1000 Angstroms.

14. A method for forming a contact etch stop layer and overlying PMD layer for selectively introducing strain into a MOSFET channel region comprising the steps of:

providing a first and second MOSFET device having a respective first polarity and second polarity opposite from the first polarity selected from the group consisting of P and N type on a semiconducting substrate;

forming a first stressed nitride contact etch stop (CESL) layer according to a mixed frequency PECVD method having a first stress type selected from the group consisting of compressive and tensile stress over the first and second MOSFET device active area;

removing a portion of the first stressed nitride CESL layer portion overlying the second MOSFET device active area;

forming a second stressed nitride CESL layer having a second stress type according to a mixed frequency PECVD method opposite the first stressed nitride layer over the first and second MOSFET device active areas;

removing a portion of the second stressed nitride CESL layer overlying the first MOSFET device active area; and

,

forming a pre-metal dielectric (PMD) layer over the first and second MOSFET device active areas having a less compressive or tensile stress.

15. The method of claim 14, wherein the mixed frequency PECVD method comprises at least two RF power sources to produce a mixed frequency signal, a first RF power source operating at a frequency of from about 300 KHz to 500 KHz and a second RF power source operating at a frequency of about 13 to 14 MHz.

16. The method of claim 14, wherein the first and second MOSFET devices further comprise metal silicide regions selected from the group consisting of cobalt silicide and nickel silicide.

17. The method of claim 14, wherein the first and second stressed nitride CESL layers are formed at a temperature of less than about 550°

C.

18. The method of claim 14, wherein first and second stressed CESL layers are selected from the group consisting of silicon nitride and silicon oxynitride.

19. The method of claim 14, wherein the PMD layer is selected from the group consisting of undoped silicate (USG) glass and phosphorous silicate glass (PSG) deposited according to a CVD method selected from the group consisting of atmospheric and sub-atmospheric CVD.

20. The method of claim 14, wherein the PMD layer is selected from the group consisting of undoped and P-doped spin-on glass (SOG).

21. The method of claim 14, wherein the stressed nitride CESL layers are formed comprising silane containing precursors selected from the group consisting of (SiH₄), disilane (Si₂H₆), trisilane (Si₃H₈), dichlorosilane (SiH₂Cl₂), trichlorosilane (SiHCl₃), and hexacholorodisilane (HCD)(Si₂Cl₆).

22. The method of claim 14, wherein the stressed nitride CESL layers are formed having a stress level absolute value greater than about 7×

10⁹ dynes/cm².

23. The method of claim 14, wherein the semiconductor substrate comprises a material selected from the group consisting of silicon, strained semiconductor, compound semiconductor, multi-layered semiconductors, silicon on strained semiconductor, silicon on insulator, and combinations thereof.

24. The method of claim 14, wherein the semiconductor substrate comprises silicon on insulator (SOI), stacked SOI (SSOI), stacked SiGe on insulator (S—

SiGeOI), SiGeOI, and GeOI, and combinations thereof.

25. The method of claim 14, wherein the stressed nitride layers are formed having a thickness from about 100 Angstroms to about 1000 Angstroms.

26. A MOSFET device pair with improved drive current comprising:

an N-type polarity MOSFET device and a P-type polarity MOSFET device disposed over respective active areas on a semiconductor substrate;

a first stressed nitride layer having a tensile stress over the N-type polarity MOSFET device active area;

a second stressed nitride layer having a compressive stress over the P-type polarity MOSFET device active area; and

,

a dielectric insulating layer overlying the respective MOSFET device active areas having a less compressive or tensile stress.

27. The MOSFET device pair of claim 26, wherein the first and second MOSFET devices further comprise metal silicide regions selected from the group consisting of cobalt silicide and nickel silicide.

28. The MOSFET device pair of claim 26, wherein first and second stressed layers are selected from the group consisting of silicon nitride and silicon oxynitride.

29. The MOSFET device pair of claim 26, wherein the dielectric insulating layer is selected from the group consisting of undoped silicate (USG) glass and phosphorous silicate glass (PSG).

30. The MOSFET device pair of claim 26, wherein the dielectric insulating layer is selected from the group consisting of undoped and P-doped spin-on glass (SOG).

31. The MOSFET device pair of claim 26, wherein the stressed nitride layers are formed having a stress level absolute value greater than about 7×

10⁹ dynes/cm².

32. The MOSFET device pair of claim 26, wherein the semiconductor substrate comprises a material selected from the group consisting of silicon, strained semiconductor, compound semiconductor, multi-layered semiconductors, silicon on strained semiconductor, silicon on insulator, and combinations thereof.

33. The MOSFET device pair of claim 26, wherein the semiconductor substrate comprises silicon on insulator (SOI), stacked SOI (SSOI), stacked SiGe on insulator (S—

SiGeOI), SiGeOI, and GeOI, and combinations thereof.

34. The MOSFET device pair of claim 26, wherein the stressed nitride layers are formed having a thickness from about 100 Angstroms to about 1000 Angstroms.