Thin film transistor array panel and manufacturing method thereof

• US 20060024895A1
• Filed: 07/27/2005
• Published: 02/02/2006
• Est. Priority Date: 07/27/2004
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Dong-Gyu
• Granted Patent: US 7,749,824 B2
• Time in Patent Office: Days
• US Class Current: 438/299
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Abstract

A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; forming a gate insulating layer on the gate line; forming a semiconductor layer on the gate insulating layer; forming an ohmic contact on the semiconductor layer; forming a data line and a drain electrode on the ohmic contact; depositing a passivation layer on the data line and the drain electrode; forming a first photoresist layer on the passivation layer; etching the passivation layer and the gate insulating layer using the first photoresist layer as a mask to expose a portion of the drain electrode and a portion of the substrate; depositing a conductive film; and removing the photoresist layer; to form a pixel electrode on a portion of the drain electrode exposed by the etching of the passivation layer.

Claims

1. A method of manufacturing a thin film transistor array panel, the method comprising:

forming a gate line on a substrate;

forming a gate insulating layer on the gate line;

forming a semiconductor layer on the gate insulating layer;

forming an ohmic contact on the semiconductor layer;

forming a data line and a drain electrode on the ohmic contact;

depositing a passivation layer on the data line and the drain electrode;

forming a first photoresist layer on the passivation layer;

etching the passivation layer and the gate insulating layer using the first photoresist layer as a mask to expose a portion of the drain electrode and a portion of the substrate;

depositing a conductive film; and

removing the first photoresist layer to form a pixel electrode on the portion of the drain electrode exposed by the etching of the passivation layer.

2. The method of claim 1, wherein:

the conductive film comprises a first portion disposed on the first photoresist layer and a remaining second portion; and

the removal of the first photoresist layer removes the first portion of the conductive film by lift off.

3. The method of claim 1, wherein the pixel electrode directly contacts the substrate.

4. The method of claim 1, wherein the exposed portion of the substrate encloses the exposed portion of the drain electrode.

5. The method of claim 4, wherein the exposed portion of the drain electrode and the exposed portion of the substrate occupy an area defined by the gate line and the data line.

6. The method of claim 1, wherein the etching of the passivation layer exposes a portion of the data line, and

further comprising:

forming a contact assistant on the exposed portion of the data line.

7. The method of claim 6, wherein the formation of the contact assistant is performed simultaneously with the formation of the pixel electrode.

8. The method of claim 1, wherein the formation of the gate insulating layer, the formation of the semiconductor layer, the formation of the ohmic contact, and the formation of the data lines and the drain electrodes comprises:

sequentially depositing a gate insulating layer, an intrinsic amorphous silicon layer, an extrinsic amorphous silicon layer, and a data conductor layer;

forming a second photoresist layer on the data conductor layer;

sequentially etching the data conductor layer, the extrinsic amorphous silicon layer, and the intrinsic silicon layer using the second photoresist layer as a mask to form a data conductor, an extrinsic semiconductor layer, and an intrinsic semiconductor layer;

transforming the second photoresist layer into a third photoresist layer; and

etching the data conductor and the extrinsic semiconductor layer to form the data line and the drain electrode and ohmic contacts.

9. The method of claim 8, wherein the second photoresist layer is formed by using a photo mask including a light blocking area, a translucent area, and a light transmitting area.

10. The method of claim 9, wherein the transformation of the second photoresist layer into the third photoresist layer comprises ashing.

11. The method of claim 1, wherein the formation of the gate insulating layer, the formation of the semiconductor layer, the formation of the ohmic contact, the formation of the data lines, and the formation of the drain electrodes is performed using single lithography step.

12. The method of claim 1, wherein the data line and the drain electrode comprise Mo or Cr.

13. The method of claim 1, wherein the pixel electrode comprises amorphous ITO or IZO.

17. The method of claim 13, wherein the semiconductor layer, the ohmic contact, the data line, and the drain electrode are formed using a single lithography step.

14. A method of manufacturing a thin film transistor array panel, the method comprising:

forming a gate line on a substrate;

forming a gate insulating layer on the gate line;

forming a semiconductor layer on the gate insulating layer;

forming an ohmic contact on the semiconductor layer;

forming a data line and a drain electrode on the ohmic contact;

depositing a passivation layer on the data line and the drain electrode;

forming a first photoresist layer;

etching the passivation layer and the gate insulating layer using the first photoresist layer as a mask to expose a portion of the substrate;

transforming the first photoresist layer into a second photoresist layer;

etching the passivation layer using the second photoresist layer as a mask to expose a portion of the drain electrode;

depositing a conductive film; and

removing the second photoresist layer to form a pixel electrode on the portion of the drain electrode exposed by the etching of the passivation layer.

15. The method of claim 14, wherein the first photoresist layer is formed by using a photo mask including a light blocking area, a translucent area, and a light transmitting area.

16. The method of claim 14, wherein the transformation of the first photoresist layer into the second photoresist layer comprises ashing.

18. The method of claim 14, wherein:

the conductive film includes a first portion disposed on the second photoresist layer and a remaining second portion; and

the removal of the second photoresist layer removes the first portion of the conductive film by lift off.

19. The method of claim 14, wherein the pixel electrode directly contacts the substrate and the gate insulating layer.

20. The method of claim 19, wherein:

the etching of the passivation layer using the second photoresist layer as a mask exposes a portion of the gate insulating layer; and

an area defined by the gate line and the data line is substantially occupied by the exposed portion of the substrate except for the exposed portion of the drain electrode and the exposed portion of the gate insulating layer.

21. The method of claim 14, wherein:

the etching of the passivation layer using the second photoresist layer exposes a portion of the data line; and

the removal of the second photoresist layer comprises forming a contact assistant on the exposed portion of the data line.

22. The method of claim 14, wherein the formation of the gate insulating layer, the formation of the semiconductor layer, the formation of the ohmic contact, and the formation of the data lines and the drain electrodes comprises:

sequentially depositing a gate insulating layer, an intrinsic amorphous silicon layer, an extrinsic amorphous silicon layer, and a data conductor layer;

forming a third photoresist layer on the data conductor layer;

sequentially etching the data conductor layer, the extrinsic amorphous silicon layer, and the intrinsic silicon layer using the third photoresist layer as a mask to form a data conductor, an extrinsic semiconductor layer, and an intrinsic semiconductor layer;

partially removing the third photoresist layer to form a fourth photoresist layer; and

etching the data conductor and the extrinsic semiconductor layer to form the data line, the drain electrode, and ohmic contacts.

23. The method of claim 22, wherein the third photoresist layer is formed by using a photo mask including a light blocking area, a translucent area, and a light transmitting area.

24. The method of claim 22, wherein the partial removal of the third photoresist layer to form the fourth photoresist layer comprises ashing.

25. A thin film transistor array panel comprising:

a gate line formed on a substrate;

a gate insulating layer formed on the gate line;

a semiconductor layer formed on the gate insulating layer;

a data line and a drain electrode formed on the semiconductor layer, the drain electrode including first and second portions;

a passivation layer formed on the data line and the first portion of the drain electrode; and

a pixel electrode formed on the substrate and the second portion of the drain electrode, said pixel electrode having edges substantially coinciding with edges of the passivation layer.

26. The thin film transistor array panel of claim 25, wherein:

the passivation layer has a contact hole exposing a portion of the data line; and

the thin film transistor array panel further comprises a contact assistant formed in the contact hole and having edges substantially coinciding with edges of the contact hole.

27. The thin film transistor array panel of claim 25, wherein the gate insulating layer has edges substantially coinciding with edges of the passivation layer except for a portion under the drain electrode.

28. The thin film transistor array panel of claim 25, wherein:

the gate insulating layer has edges substantially coinciding with edges of the passivation layer except for a portion around the drain electrode; and

the portion around the drain electrode is exposed.

29. The thin film transistor array panel of claim 28, wherein the exposed portion of the gate insulating layer is covered with the pixel electrode.

30. The thin film transistor array panel of claim 25, wherein the semiconductor layer has substantially the same planar shape as the data line and the drain electrode except for a portion disposed between the data line and the drain electrode.

31. The thin film transistor array panel of claim 25, wherein the pixel electrode includes a cutout.

32. The thin film transistor array panel of claim 31, further comprising a storage electrode comprised of the same layer as the gate line and overlapping the pixel electrode.

33. The thin film transistor array panel of claim 32, further comprising a storage conductor formed on the gate insulating layer, connected to the pixel electrode, and overlapping the storage electrode.