Deep alignment marks on edge chips for subsequent alignment of opaque layers

• US 20060024923A1
• Filed: 08/02/2004
• Published: 02/02/2006
• Est. Priority Date: 08/02/2004
• Status: Active Grant

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Qimonda AG (Infineon Technologies AG)
• Inventors: Sarma, Chandrasekhar, Kasko, Ihar
• Granted Patent: US 7,442,624 B2
• Time in Patent Office: Days
• US Class Current: 438/462
• CPC Class Codes: H01L 2223/5442 comprising non digital, non alphanumeric information, e.g. symbols
• CPC Class Codes: H01L 2223/54466 Located in a dummy or reference die
• CPC Class Codes: H01L 2223/5448 Located on chip prior to dicing and remaining on chip after dicing
• CPC Class Codes: H01L 2223/54493 Peripheral marks on wafers, e.g. orientation flats, notches, lot number
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 61/00 Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices

Abstract

A method of forming alignment marks on edge chips in a kerf region of a semiconductor workpiece. The alignment marks are formed in at least one material layer of the semiconductor device. The alignment marks are formed using a separate lithography mask, and may extend into lower layers, including the workpiece, of the semiconductor device. An opaque material layer is deposited, and depressions are formed in the opaque layer over the deep alignment mark trenches. The depressions in the opaque material layer are used to align a lithography process to open the opaque material layer over alignment marks in an underlying metallization layer. The alignment marks in the metallization layer are then used to align the lithography process used to pattern the opaque material layer.

Claims

1. A method of manufacturing a semiconductor device, comprising:

providing a workpiece, the workpiece including a plurality of die regions and a kerf region, each die region including an alignment mark region and a component region;

forming a first insulating layer over the workpiece;

forming at least one first alignment mark over the alignment mark region of each die region and a plurality of first conductive lines over the component region of each die region within the first insulating layer, wherein forming the at least one first alignment mark comprises filling the at least one first alignment mark with a conductive material;

forming at least one second alignment mark within at least the first insulating layer over the kerf region of the workpiece, the at least one second alignment mark comprising a trench having a bottom and sidewalls;

depositing an opaque material layer over the at least one second alignment mark and the first insulating layer, the opaque material layer lining the bottom and sidewalls of the trench of the at least one second alignment mark, leaving a depression in the opaque material layer over each at least one second alignment mark;

depositing a first masking layer over the opaque material layer;

patterning the first masking layer using a lithography mask or tool, removing the first masking layer from over the at least one first alignment mark, using the depression over the at least one second alignment mark to align the lithography mask or tool used to pattern the first masking layer over the opaque material layer;

removing the opaque material layer from over the at least one first alignment mark using the first masking layer as a mask;

removing the first masking layer;

depositing a second masking layer over the opaque material layer and the at least one first alignment mark;

patterning the second masking layer with a pattern for the opaque material layer in the component region of each die region using the at least one first alignment mark for alignment; and

patterning the opaque material layer using the second masking layer as a mask.

2. The method according to claim 1, wherein the first masking layer or the second masking layer comprise a photoresist, or a hard mask and a photoresist.

3. The method according to claim 1, further comprising, after forming the at least one second alignment mark:

forming a second insulating layer over the at least one second alignment mark, the at least one first alignment mark, the plurality of first conductive lines, and the first insulating layer;

patterning the second insulating layer with a via pattern;

depositing a conductive material layer over the patterned second insulating layer; and

removing the conductive material layer from over a top surface of the second insulating layer, leaving a conductive via formed in the second insulating layer over the component region of each die region and leaving the conductive material layer lining the second insulating layer within the at least one second alignment mark, wherein depositing the opaque material layer comprises depositing the opaque material layer over the conductive material over each at least one second alignment mark.

4. The method according to claim 1, wherein forming the at least one second alignment mark comprises forming at least one set of second alignment marks.

5. The method according to claim 4, wherein the kerf region of the workpiece comprises a plurality of incomplete die or a plurality of unused workpiece areas, wherein forming the at least one second alignment mark comprises forming at least one set of alignment marks in at least two incomplete die or unused workpiece areas in the kerf region.

6. The method according to claim 5, wherein forming the at least one set of second alignment marks comprises forming a first set of second alignment marks along a top edge or a bottom edge of the incomplete die or unused workpiece areas in the kerf region, and forming a second set of second alignment marks along a vertical side edge of the incomplete die or unused workpiece areas in the kerf region.

7. The method according to claim 6, wherein forming the second alignment marks comprises forming second alignment marks having a width of about 2 μ

m or less and a length of about 60 μ

m or less.

8. The method according to claim 6, wherein the first set of second alignment marks comprises about 10 or more second alignment marks, and wherein the second set of alignment marks comprises about 10 or more second alignment marks.

9. The method according to claim 1, wherein forming the at least one second alignment mark within at least the second insulating layer comprises forming the at least one second alignment mark in at least the entire thickness of the first insulating layer.

10. The method according to claim 1, further comprising forming at least one third insulating layer over the workpiece, before forming the first insulating layer, wherein forming the at least one second alignment mark further comprises forming the at least one second alignment mark within at least a portion of the at least one third insulating layer.

11. The method according to claim 10, wherein forming the at least one second alignment mark comprises forming the at least one second alignment mark within the entire thickness of one of the at least one third insulating layer.

12. The method according to claim 11, wherein forming the at least one second alignment mark further comprises forming the at least one second alignment mark within the entire thickness of each at least one third insulating layer.

13. The method according to claim 12, wherein forming the at least one second alignment mark further comprises forming the at least one second alignment mark within a top portion of the workpiece.

14. The method according to claim 1, wherein forming the at least one second alignment mark comprises forming the at least one second alignment mark having a depth of at least about 8,000 Angstroms.

15. The method according to claim 1, wherein forming the at least one second alignment mark comprises forming the at least one second alignment mark having a depth of about 3 μ

m or less.

16. The method according to claim 1, wherein the semiconductor device comprises a magnetic random access memory (MRAM) device, wherein the alignment mark region comprises a kerf or edge region of each die region of the MRAM device, wherein the component region comprises an array region of the MRAM device, wherein the depositing the opaque material layer comprises depositing a first magnetic stack, and wherein patterning the opaque material layer comprises forming at least one magnetic tunnel junction (MTJ).

17. The method according to claim 16, further comprising, after forming the at least one second alignment mark:

forming a second insulating layer over the at least one second alignment mark, the at least one first alignment mark, the plurality of first conductive lines, and the first insulating layer;

patterning the second insulating layer with a via pattern;

depositing a conductive material layer over the patterned second insulating layer; and

removing the conductive material layer from over a top surface of the second insulating layer, leaving a conductive via formed in the second insulating layer over the component region of each die region and leaving the conductive material layer lining the second insulating layer within the at least one second alignment mark, wherein depositing the opaque material layer comprises depositing the opaque material layer over the conductive material over each at least one second alignment mark.

18. The method according to claim 16, further comprising:

depositing a second magnetic stack over at least the MTJ, the second magnetic stack comprising an opaque material;

depositing a third masking layer over the second magnetic stack;

patterning the third masking layer using a lithography mask or tool, using the depression over the at least one second alignment mark to align the lithography mask or tool used to pattern the second masking layer over the second magnetic stack;

removing the second magnetic stack from over the at least one first alignment mark using the third masking layer as a mask;

removing the third masking layer;

depositing a fourth masking layer over the second magnetic stack and the at least one first alignment mark;

patterning the fourth masking layer with a pattern for the second magnetic stack using the at least one first alignment mark for alignment; and

patterning the second magnetic stack using the fourth masking layer as a mask.

19. The method according to claim 16, wherein the first magnetic stack comprises a first magnetic layer, a tunnel barrier disposed over the first magnetic layer, and a second magnetic layer disposed over the tunnel barrier, wherein at least the second magnetic layer comprises an opaque material, further comprising forming a plurality of second conductive lines over each at least one MTJ.

20. The method according to claim 1, further comprising forming at least one second alignment mark within at least the first insulating layer over at least one of the plurality of die region of the workpiece, wherein a die region having the at least one second alignment mark formed therein comprises a non-functioning chip.

21. A method of manufacturing a magnetic memory device, comprising:

providing a workpiece, the workpiece including a plurality of die regions and a kerf region, each die region comprising an alignment mark region at the edges thereof, and an array region disposed within the alignment mark region;

forming a first insulating layer over the workpiece;

forming at least one first alignment mark over the alignment mark region of each die region and a plurality of first conductive lines over the array region of each die region within the first insulating layer, wherein forming the at least one first alignment mark comprises filling the at least one first alignment mark with a conductive material;

forming at least one second alignment mark within at least the first insulating layer over the kerf region of the workpiece, the at least one second alignment mark comprising a trench having a bottom and sidewalls;

forming a second insulating layer over the at least one second alignment mark, the at least one first alignment mark, the plurality of first conductive lines, and the first insulating layer, wherein the second insulating layer lines the bottom and sidewalls of the at least one second alignment mark trench;

forming a conductive via in the second insulating layer over the array region of each die region using a damascene process, wherein the conductive via material lines the second insulating layer lining the at least one second alignment mark bottom and sidewalls;

depositing a first magnetic stack over the conductive via and the second insulating layer, wherein a depression is formed in the first magnetic stack over each at least one second alignment mark;

depositing a first masking layer over the first magnetic stack;

patterning the first masking layer using a lithography mask or tool, removing the first masking layer from over the at least one first alignment mark, using the depression in the first magnetic stack over the at least one second alignment mark to align the lithography mask or tool used to pattern the first masking layer over the first magnetic stack;

removing the first magnetic stack from over the at least one first alignment mark using the first masking layer as a mask, leaving the at least one first alignment mark exposed;

removing the first masking layer;

depositing a second masking layer over the first magnetic stack and the at least one first alignment mark;

patterning the second masking layer with a pattern for the first magnetic stack in the array region of each die region using the at least one first alignment mark for alignment; and

patterning the first magnetic stack using the second masking layer as a mask, wherein the patterned first magnetic stack comprises a magnetic memory cell.

22. The method according to claim 21, wherein the kerf region comprises a plurality of incomplete die or a plurality of unused workpiece areas, wherein forming the at least one second alignment mark comprises forming at least one set of alignment marks in at least two incomplete die or unused workpiece areas in the kerf region.

23. The method according to claim 21, wherein forming the at least one set of second alignment marks comprises forming a first set of second alignment marks along a top edge or a bottom edge of the incomplete die or unused workpiece areas in the kerf region, and forming a second set of second alignment marks along a vertical side edge of the incomplete die or unused workpiece areas in the kerf region.

24. The method according to claim 23, wherein forming the second alignment marks comprise forming second alignment marks having a width of about 2 μ

m or less and a length of about 60 μ

m or less, and wherein the first set of second alignment marks comprises about 10 or more second alignment marks, and wherein the second set of alignment marks comprises about 10 or more second alignment marks.

25. The method according to claim 21, wherein forming the at least one second alignment mark within at least the first insulating layer comprises forming the at least one second alignment mark in at least the entire thickness of the first insulating layer, or forming the at least one second alignment mark within a top portion of the workpiece.

26. The method according to claim 25, wherein the workpiece further comprises at least one third insulating layer disposed between the workpiece and the first insulating layer, wherein forming the at least one second alignment mark comprises forming the at least one second alignment mark within at least a portion of at least one of the third insulating layers.

27. The method according to claim 21, wherein forming the at least one second alignment mark comprises forming the at least one second alignment mark having a depth of at least about 8,000 Angstroms.

28. The method according to claim 21, wherein forming the at least one second alignment mark comprises forming the at least one second alignment mark having a depth of about 3 μ

m or less.

29. The method according to claim 21, wherein the magnetic memory device comprises a magnetic random access memory (MRAM) device, and wherein patterning the magnetic stack comprises forming at least one magnetic tunnel junction (MTJ).

30. The method according to claim 29, further comprising:

depositing a second magnetic stack over at least the MTJ, the second magnetic stack comprising an opaque material;

depositing a third masking layer over the second magnetic stack;

patterning the third masking layer using a lithography mask or tool, using the depression over the at least one second alignment mark to align the lithography mask or tool used to pattern the second masking layer over the second magnetic stack;

removing the second magnetic stack from over the at least one first alignment mark using the third masking layer as a mask;

removing the third masking layer;

depositing a fourth masking layer over the second magnetic stack and the at least one first alignment mark;

patterning the fourth masking layer with a pattern for the second magnetic stack using the at least one first alignment mark for alignment; and

patterning the second magnetic stack using the fourth masking layer as a mask.

31. The method according to claim 29, wherein the first magnetic stack comprises a first magnetic layer, a tunnel barrier disposed over the first magnetic layer, and a second magnetic layer disposed over the tunnel barrier, wherein at least the second magnetic layer comprises an opaque material, further comprising forming a plurality of second conductive lines over each at least one MTJ.

32. A method of forming alignment marks of a semiconductor workpiece, the method comprising:

providing a semiconductor workpiece, the workpiece including a plurality of die regions and at least one kerf region, the at least one kerf region comprising regions where die is not formed or where incomplete die is formed, the workpiece including at least one material layer disposed thereon;

forming a first set of alignment marks in a first kerf region; and

forming a second set of alignment marks in a second kerf region, wherein the first set of alignment marks and the second set of alignment marks extend at least about 8,000 Angstroms into the at least one material layer disposed on the workpiece, or into the at least one material layer and the workpiece.

33. A semiconductor workpiece, the workpiece including a plurality of die regions and at least one kerf region, the at least one kerf region comprising regions where die is not formed or where incomplete die is formed, the workpiece including at least one material layer disposed thereon, the workpiece comprising:

a first set of alignment marks in a first kerf region; and

a second set of alignment marks in a second kerf region, wherein the first set of alignment marks and the second set of alignment marks extend at least about 8,000 Angstroms into the at least one material layer disposed on the workpiece, or into the at least one material layer and the workpiece.

34. The semiconductor workpiece according to claim 33, wherein the first set of alignment marks and the second set of alignment marks extend about 3 μ

m into the at least one material layer disposed on the workpiece, or into the at least one material layer and the workpiece.

35. The semiconductor workpiece according to claim 33, wherein each alignment mark comprises a width of about 2 μ

m or less and a length of about 60 μ

m or less, wherein the first set of alignment marks comprise about 10 or more alignment marks, and wherein the second set of alignment marks comprises about 10 or more alignment marks.

36. The semiconductor workpiece according to claim 33, wherein the first set of alignment marks comprises a plurality of alignment marks disposed along a top edge or a bottom edge of the first kerf region, and wherein the second set of alignment marks comprises a plurality of alignment marks disposed along a vertical side edge of the second kerf region.

37. The semiconductor workpiece according to claim 33, further comprising a third set of alignment marks in at least one of the plurality of die regions, wherein a die region having the third set of alignment marks comprises a non-functioning chip.