Semiconductor processing methods of forming integrated circuitry and semiconductor processing methods of forming dynamic random access memory (DRAM) circuitry

• US 20060024933A1
• Filed: 09/26/2005
• Published: 02/02/2006
• Est. Priority Date: 08/27/1998
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Juengling, Werner
• Granted Patent: US 7,235,480 B2
• Time in Patent Office: Days
• US Class Current: 438/542
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells

Abstract

Semiconductor processing methods of forming integrated circuitry, and in particular, dynamic random access memory (DRAM) circuitry are described. In one embodiment, a single masking step is utilized to form mask openings over a substrate, and both impurities are provided and material of the substrate is etched through the openings. In one implementation, openings are contemporaneously formed in a photo masking layer over substrate areas where impurities are to be provided, and other areas where etching is to take place. In separate steps, the substrate is doped with impurities, and material of the substrate is etched through the mask openings. In another implementation, two conductive lines are formed over a substrate and a masking layer is formed over the conductive lines. Openings are formed in the masking layer in the same step, with one of the openings being received over one conductive line, and another of the openings being received over the other conductive line. Impurities provided through an opening into the substrate proximate one conductive line, and material from over the other conductive line is removed through the other opening to at least partially form a contact opening over the other conductive line.

Claims

1. A semiconductor processing method comprising, in a single masking step, doping impurities into a substrate through openings formed in a mask layer, and etching material of the substrate through said openings.

2. The semiconductor processing method of claim 1 further comprising doping the impurities into the substrate prior to etching the substrate material.

3. The semiconductor processing method of claim 1, wherein some of the openings have different transverse cross-sectional dimensions than other of the openings.

4. The semiconductor processing method of claim 1, wherein the substrate comprises a bulk monocrystalline substrate and the openings are dimensioned to permit some of the impurity to be received by the substrate as diffusion regions only through some of the openings.

5. The semiconductor processing method of claim 1, wherein two openings are received over individual conductive lines which are covered with insulative material, and the etching of the substrate material comprises etching portions of the insulative material.

6. The semiconductor processing method of claim 5, wherein the etching comprises isotropically etching said insulative material.

7. The semiconductor processing method of claim 5, wherein the etching comprises anisotropically etching said insulative material.

8. The semiconductor processing method of claim 5, wherein the insulative material comprises first and second different insulative material, and the etching comprises selectively etching one relative to the other.

9. The semiconductor processing method of claim 8, wherein the one insulative material comprises a nitride material.

10. A semiconductor processing method of forming integrated circuitry comprising:

forming a photomasking layer over a substrate;

contemporaneously forming openings in the photomasking layer over substrate areas where impurities are to be provided, and other substrate areas where etching is to take place; and

in separate steps, doping the substrate with impurities through said openings and etching the substrate through said openings.

11. The semiconductor processing method of claim 10 further comprising doping the substrate prior to etching the substrate.

12. The semiconductor processing method of claim 10, wherein one opening is formed over a conductive line, and further comprising providing impurities into the substrate proximate the conductive line.

13. The semiconductor processing method of claim 10, wherein the substrate comprises a bulk substrate, and further comprising providing impurities through the openings, the openings being dimensioned to permit formation of diffusion regions within the bulk substrate proximate only some of the openings.

14. The semiconductor processing method of claim 10 further comprising etching substrate material through all of the openings.

15. The semiconductor processing method of claim 10, wherein the forming of the openings comprises forming two spaced-apart openings over first and second different insulative materials, and further comprising selectively etching one of the insulative materials within the openings relative to the other of the insulative materials within the openings.

16. The semiconductor processing method of claim 15, wherein the etching comprises isotropically etching said material.

17. The semiconductor processing method of claim 15, wherein the etching comprises anisotropically etching said material.

18. A semiconductor processing method of forming integrated circuitry comprising:

forming two conductive lines over a substrate;

forming a masking layer over the two conductive lines;

forming two openings through the masking layer in. the same step, one of the openings being received over one conductive line, another of the openings being received over the other conductive line;

providing impurity through the one opening and into the substrate proximate the one conductive line; and

removing material over the other conductive line through the other opening to at least partially form a contact opening over the other conductive line.

19. The semiconductor processing method of claim 18, wherein the forming of the two openings comprises forming the one opening to have a larger transverse cross-section than the other of the openings.

20. The semiconductor processing method of claim 18, wherein the removing comprises removing material from over both conductive lines.

21-32. -32. (canceled)