Method of manufacturing semiconductor device

• US 20060024949A1
• Filed: 07/28/2005
• Published: 02/02/2006
• Est. Priority Date: 07/29/2004
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Yamada, Hiroshi, Yamaguchi, Keiichi
• Granted Patent: US 7,557,017 B2
• Time in Patent Office: Days
• US Class Current: 438/622
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2224/02371 connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/02377 Fan-in arrangement
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05023 the whole internal layer protruding from the surface
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/10 Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01011 : Sodium [Na]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01072 : Hafnium [Hf]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys

Abstract

The invention is directed to improvement of reliability of a process of separating a layer to be patterned such as a wiring layer in a semiconductor device manufacturing method. A wiring layer is formed on a back surface of a semiconductor substrate including an opening. A third resist layer (positive resist layer) is formed on the wiring layer, having an opening in a predetermined region along a dicing line at a bottom of the opening, and the wiring layer is etched using the third resist layer as a mask. After the third resist layer is removed, a fourth resist layer (negative resist layer) is formed on the wiring layer so as to leave the wiring layer in a region of a predetermined pattern, and the wiring layer is etched using the fourth resist layer as a mask. The wiring layer is thus patterned so as to form the predetermined pattern and be separated at the predetermined region along the dicing line at the bottom of the opening without fail.

Claims

1. A method of manufacturing a semiconductor device, comprising:

providing a semiconductor substrate;

forming a recess in the substrate along a dicing line of the substrate by etching the substrate from a back surface thereof;

forming a layer that is disposed in the recess and on the back surface of the substrate;

forming a first resist layer on the layer so that the first resist layer has an opening at a predetermined location of a bottom of the recess;

etching the layer using the first resist layer as a mask so as to form a corresponding opening in the layer;

removing the first resist layer to expose the layer;

forming on the exposed layer a second resist layer that corresponds to a predetermined pattern and covers the opening of the layer; and

etching the layer using the second resist layer as a mask so that the predetermined pattern is reflected in the layer.

2. The method of claim 1, wherein the first resist layer is a positive resist layer and the second resist layer is a negative resist layer.

3. A method of manufacturing a semiconductor device, comprising:

providing a semiconductor substrate;

forming a recess in the substrate along a dicing line of the substrate by etching the substrate from a back surface thereof;

forming a layer that is disposed in the recess and on the back surface of the substrate;

forming on the layer a first resist layer that corresponds to a predetermined pattern;

etching the layer using the first resist layer as mask so that the predetermined pattern is reflected in the layer;

removing the first resist layer to expose the patterned layer;

forming on the patterned layer a second resist layer that has an opening at a predetermined location of a bottom of the recess; and

etching the patterned layer using the second resist layer as a mask so as to form a corresponding opening in the patterned layer.

4. The method of claim 3, wherein the first resist layer is a negative resist layer and the second resist layer is a positive resist layer.

5. A method of manufacturing a semiconductor device, comprising:

providing a semiconductor substrate comprising a first insulation film formed on a front surface of the substrate and a pad electrode formed on the first insulation film along a dicing line of the substrate;

attaching a support body to the front surface of the substrate;

forming a recess in the substrate along the dicing line by etching the substrate from a back surface thereof, the recess corresponding to the entire length of the dicing line or part of the length;

forming a second insulation film to cover the recess and the back surface of the substrate;

etching the first and second insulation films at a bottom of the recess so that part of the pad electrode is exposed;

forming a wiring layer that is disposed in the recess and on the back surface of the substrate and connected with the exposed pad electrode;

forming a first resist layer on the wiring layer so that the first resist layer has an opening at a predetermined location of the bottom of the recess;

etching the wiring layer using the first resist layer as a mask so as to form a corresponding opening in the wiring layer;

removing the first resist layer to expose the wiring layer;

forming on the exposed wiring layer a second resist layer that corresponds to a predetermined pattern and covers the opening of the wiring layer; and

etching the wiring layer using the second resist layer as a mask so that the predetermined pattern is reflected in the wiring layer.

6. The method of claim 5, wherein the first resist layer is a positive resist layer and the second resist layer is a negative resist layer.

7. The method of claim 5, further comprising forming a protection layer on the back surface of the substrate so that part of the wiring layer is exposed in an opening formed in the protection layer, and forming a conductive terminal on the exposed part of the wiring layer.

8. The method of claim 5, further comprising cutting along the dicing line to produce a semiconductor dice.

9. The method of claim 6, further comprising forming a protection layer on the back surface of the substrate so that part of the wiring layer is exposed in an opening formed in the protection layer, and forming a conductive terminal on the exposed part of the wiring layer.

10. The method of claim 6, further comprising cutting along the dicing line to produce a semiconductor dice.

11. The method of claim 7, further comprising cutting along the dicing line to produce a semiconductor dice.

12. The method of claim 9, further comprising cutting along the dicing line to produce a semiconductor dice.

13. A method of manufacturing a semiconductor device, comprising:

providing a semiconductor substrate comprising a first insulation film formed on a front surface of the substrate and a pad electrode formed on the first insulation film along a dicing line of the substrate;

attaching a support body to the front surface of the substrate;

forming a recess in the substrate along the dicing line by etching the substrate from a back surface thereof, the recess corresponding to the entire length of the dicing line or part of the length;

forming a second insulation film to cover the recess and the back surface of the substrate;

etching the first and second insulation films at a bottom of the recess so that part of the pad electrode is exposed;

forming a wiring layer that is disposed in the recess and on the back surface of the substrate and connected with the exposed pad electrode;

forming on the wiring layer a first resist layer that corresponds to a predetermined pattern;

etching the wiring layer using the first resist layer as mask so that the predetermined pattern is reflected in the wiring layer;

removing the first resist layer to expose the patterned wiring layer;

forming on the patterned wiring layer a second resist layer that has an opening at a predetermined location of the bottom of the recess; and

etching the patterned wiring layer using the second resist layer as a mask so as to form a corresponding opening in the patterned wiring layer.

14. The method of claim 13, wherein the first resist layer is a negative resist layer and the second resist layer is a positive resist layer.

15. The method of claim 13, further comprising forming a protection layer on the back surface of the substrate so that part of the wiring layer is exposed in an opening formed in the protection layer, and forming a conductive terminal on the exposed part of the wiring layer.

16. The method of claim 13, further comprising cutting along the dicing line to produce a semiconductor dice.

17. The method of claim 14, further comprising forming a protection layer on the back surface of the substrate so that part of the wiring layer is exposed in an opening formed in the protection layer, and forming a conductive terminal on the exposed part of the wiring layer.

18. The method of claim 14, further comprising cutting along the dicing line to produce a semiconductor dice.

19. The method of claim 15, further comprising cutting along the dicing line to produce a semiconductor dice.

20. The method of claim 17, further comprising cutting along the dicing line to produce a semiconductor dice.