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Dual damascene diffusion barrier/liner process with selective via-to-trench-bottom recess

  • US 20060024953A1
  • Filed: 07/29/2004
  • Published: 02/02/2006
  • Est. Priority Date: 07/29/2004
  • Status: Abandoned Application
First Claim
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1. A method of fabricating an integrated circuit, comprising the steps of:

  • forming a dielectric layer;

    forming a trench and a via in said dielectric layer;

    depositing a first barrier layer over said dielectric layer including in said trench and said via;

    performing a re-sputter etch in a physical vapor deposition tool with an intermediate DC target power, wherein the re-sputter etch results in a higher etch rate at a bottom of said via than at a bottom of said trench;

    depositing a second barrier layer over said first barrier layer.

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