Copper damascene barrier and capping layer

• US 20060024954A1
• Filed: 08/02/2004
• Published: 02/02/2006
• Est. Priority Date: 08/02/2004
• Status: Abandoned Application

• Current Assignee: Lain-Jong Li, Syun-Ming Jang, Yung-Chen Lu, Zhen-Cheng Wu
• Original Assignee: Lain-Jong Li, Syun-Ming Jang, Yung-Chen Lu, Zhen-Cheng Wu
• Inventors: Li, Lain-Jong, Wu, Zhen-Cheng, Lu, Yung-Chen, Jang, Syun-Ming
• Application Number:
  US10/910,007
• Publication Number:
  US 20060024954A1
• Time in Patent Office: Days
• US Class Current: 438/629
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation
• CPC Class Codes: H01L 21/76846 Layer combinations

Abstract

A method for forming a damascene with improved electrical properties and resulting structure thereof including providing at least one dielectric insulating layer overlying a first etch stop layer; forming an anti-reflectance coating (ARC) layer prior to a photolithographic patterning process; forming at least one opening extending through a thickness portion of the at least one dielectric insulating layer and first etch stop layer according to said photolithographic patterning and an etching process; blanket depositing a barrier layer including material selected from the group consisting of silicon carbide and silicon oxycarbide to line the at least one opening; blanket depositing a refractory metal liner over the barrier layer; blanket depositing at least one metal layer to fill the at least one opening; and, removing at least the at least one metal layer overlying the at least one opening level according to a chemical mechanical polish (CMP) process.

Claims

1. A method for forming a damascene with improved electrical properties comprising the steps of:

providing at least one dielectric insulating layer overlying a first etch stop layer;

forming at least one opening extending through a thickness portion of the at least one dielectric insulating layer and first etch stop layer;

depositing a barrier layer comprising a material selected from the group consisting of silicon carbide and silicon oxycarbide to line the at least one opening;

depositing a refractory metal liner over the barrier layer;

depositing at least one metal layer to fill the at least one opening; and

,

removing at least the at least one metal layer overlying the at least one opening level according to a chemical mechanical polish (CMP) process.

2. The method of claim 1, wherein a silicon carbide polishing stop layer is formed overlying and contacting the at least one dielectric insulating layer prior to forming an ARC layer overlying and contacting said polishing stop layer.

3. The method of claim 2, wherein the ARC layer is an inorganic ARC layer comprising silicon oxynitride left in place following the step of forming at least one opening.

4. The method of claim 2, wherein the barrier layer comprises silicon oxycarbide.

5. The method of claim 2, wherein said CMP process stops on said silicon carbide polishing stop layer.

6. The method of claim 1, wherein the ARC layer is an organic ARC layer which is removed following the step of forming the at least one opening.

7. The method of claim 6, wherein the barrier layer comprises silicon carbide formed to overlie and contact said at least one dielectric insulating layer wherein said CMP process stops on said silicon carbide barrier layer.

8. The method of claim 1, wherein the metal is selected from the group consisting of copper, aluminum, tantalum, and alloys thereof.

9. The method of claim 1, wherein the refractory metal liner is formed at a thickness of from about 40 Angstroms to about 60 Angstroms.

10. The method of claim 9, wherein the refractory metal liner is selected from the group consisting of tantalum and titanium.

11. The method of claim 9, wherein the refractory metal liner consists primarily of tantalum.

12. The method of claim 1, wherein the at least one dielectric insulating layer comprises a dielectric insulating layer selected from the group consisting of carbon doped oxide formed from organo-silane precursors.

13. A method for forming a damascene with improved electrical properties comprising the steps of:

providing an IMD layer comprising carbon doped oxide overlying a first etching stop layer;

forming a capping layer comprising a material selected from the group consisting of silicon carbide and silicon oxycarbide overlying and contacting said IMD layer;

forming an anti-reflectance coating (ARC) layer comprising silicon oxynitride overlying and contacting the capping layer;

forming at least one opening extending through a thickness of said IMD layer and said first etch stop layer;

depositing a barrier layer comprising a material selected from the group consisting of silicon carbide and silicon oxycarbide lining said at least one opening;

depositing a liner of tantalum over the silicon oxycarbide barrier layer;

depositing a copper layer filling said at least one opening; and

,

removing layers overlying the capping layer by a chemical mechanical polish (CMP) process.

14. The method of claim 13, wherein the IMD layer comprises a dielectric constant of less than about 3.2.

15. The method of claim 13, wherein the line width of the at least one opening is less than or equal to about 0.25 microns.

16. The method of claim 13, wherein the capping layer is formed at a thickness of from about 300 Angstroms to about 500 Angstroms.

17. The method of claim 13, wherein the barrier layer is formed at a thickness of from about 100 Angstroms to about 300 Angstroms.

18. A method for forming a damascene with improved electrical properties comprising the steps of:

providing an IMD layer comprising carbon doped oxide overlying a first etching stop layer;

forming an organic anti-reflectance coating (ARC) layer overlying and contacting the IMD layer;

forming at least one opening extending through a thickness of said IMD layer and first etch stop layer;

removing the organic ARC layer;

blanket depositing a barrier layer comprising a material elected from the group consisting of silicon carbide and silicon oxycarbide to line the at least one opening and to overlie and contact the IMD layer;

depositing a liner of tantalum over the silicon carbide barrier layer;

depositing a copper layer to fill the at least one opening; and

,

removing layers overlying the barrier layer according to a chemical mechanical polish (CMP) process.

19. The method of claim 18, wherein the IMD layer comprises a dielectric constant of less than about 3.2.

20. The method of claim 18, wherein the line width of the at least one opening is less than or equal to about 0.25 microns.

21. The method of claim 18, wherein the barrier layer is formed at a thickness of from about 100 Angstroms to about 300 Angstroms.

22. A damascene structure with an improved barrier layer and polishing stop comprising:

at least one metal filled opening extending through a thickness portion of at least one dielectric insulating layer;

said at least one metal filled opening lined with a barrier layer comprising a material selected from the group consisting of silicon carbide and silicon oxycarbide;

wherein, the at least one metal filled opening comprises an upper opening level adjacent to a polishing stop layer comprising a material selected from the group consisting of silicon carbide and silicon oxycarbide overlying and contacting the at least one dielectric insulating layer.

23. The damascene structure of claim 22, wherein the metal is selected from the group consisting of copper, aluminum, tantalum, and alloys thereof.

24. The damascene structure of claim 22, wherein the barrier layer further comprises an uppermost layer of refractory metal selected from the group consisting of tantalum and titanium.

25. The damascene structure of claim 24, wherein the uppermost layer of refractory metal is from about 40 Angstroms to about 60 Angstroms thick.

26. The damascene structure of claim 22, wherein the barrier layer is from about 100 Angstroms to about 300 Angstroms thick.

27. The damascene structure of claim 22, wherein the polishing stop layer is from about 300 Angstroms to about 500 Angstroms thick.

28. The damascene structure of claim 22, wherein the polishing stop layer and the barrier layer comprise a continuous layer having a thickness of from about 100 Angstroms to about 300 Angstroms thick.

29. The damascene structure of claim 22, wherein the at least one dielectric insulating layer comprises a dielectric constant of less than about 3.2.

30. The damascene structure of claim 22, wherein the line width of the at least one metal filled opening is less than or equal to about 0.25 microns.

31. The damascene structure of claim 22, wherein the polishing stop layer comprises silicon carbide and the barrier layer comprises silicon oxycarbide.

32. The damascene structure of claim 22, wherein the polishing stop layer and the barrier layer comprise a continuous layer of silicon carbide.